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1. 发明申请

US20060228884A1 Unidirectionally conductive materials for interconnection 有权
标题翻译：用于互连的单向导电材料
公开(公告)号：US20060228884A1
公开(公告)日：2006-10-12
申请号：US11321127
申请日：2005-12-28
申请人： Reza Golzarian , Robert Meagley , Seiichi Morimoto , Mansour Moinpour
发明人： Reza Golzarian , Robert Meagley , Seiichi Morimoto , Mansour Moinpour
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.
摘要翻译：描述了一种形成方法和包括具有单向导电材料的互连结构的器件。单向导电材料可以覆盖互连材料，和/或可以围绕互连材料，例如通过衬套沟槽和通孔的壁和底座。单向导电材料可以被配置为在对应于与接触点的突出物相对应的方向上导电，并且覆盖在单向导电材料上方的导电材料，但是在其它方向上没有实质的导电性。此外，单向导电材料可以在垂直于其形成的表面的方向或沿着或跨平面的方向上导电，但在其它方向上不具有实质的导电性。最后，单向导电材料可能具有倾向于减少金属扩散，减少电子迁移，提供粘附或粘结和/或用作蚀刻停止的性质。

2. 发明申请

US20050070096A1 Unidirectionally conductive materials for interconnection 失效
标题翻译：用于互连的单向导电材料
公开(公告)号：US20050070096A1
公开(公告)日：2005-03-31
申请号：US10676294
申请日：2003-09-30
申请人： Reza Golzarian , Robert Meagley , Seiichi Morimoto , Mansour Moinpour
发明人： Reza Golzarian , Robert Meagley , Seiichi Morimoto , Mansour Moinpour
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.
摘要翻译：描述了一种形成方法和包括具有单向导电材料的互连结构的器件。单向导电材料可以覆盖互连材料，和/或可以围绕互连材料，例如通过衬套沟槽和通孔的壁和底座。单向导电材料可以被配置为在对应于与接触点的突出物相对应的方向上导电，并且覆盖在单向导电材料上方的导电材料，但是在其它方向上没有实质的导电性。此外，单向导电材料可以在垂直于其形成的表面的方向或沿着或跨平面的方向上导电，但在其它方向上不具有实质的导电性。最后，单向导电材料可能具有倾向于减少金属扩散，减少电子迁移，提供粘附或粘结和/或用作蚀刻停止的性质。

3. 发明授权

US07084053B2 Unidirectionally conductive materials for interconnection 失效
公开(公告)号：US07084053B2
公开(公告)日：2006-08-01
申请号：US10676294
申请日：2003-09-30
申请人： Reza M. Golzarian , Robert P. Meagley , Seiichi Morimoto , Mansour Moinpour
发明人： Reza M. Golzarian , Robert P. Meagley , Seiichi Morimoto , Mansour Moinpour
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.

4. 发明授权

US07405419B2 Unidirectionally conductive materials for interconnection 有权
标题翻译：用于互连的单向导电材料
公开(公告)号：US07405419B2
公开(公告)日：2008-07-29
申请号：US11321127
申请日：2005-12-28
申请人： Reza M. Golzarian , Robert P. Meagley , Seiichi Morimoto , Mansour Moinpour
发明人： Reza M. Golzarian , Robert P. Meagley , Seiichi Morimoto , Mansour Moinpour
IPC分类号： H01L47/00 , H01L23/52
CPC分类号： H01L21/76843 , H01L21/76849 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.
摘要翻译：描述了一种形成方法和包括具有单向导电材料的互连结构的器件。单向导电材料可以覆盖互连材料，和/或可以围绕互连材料，例如通过衬套沟槽和通孔的壁和底座。单向导电材料可以被配置为在对应于与接触点的突出物相对应的方向上导电，并且覆盖在单向导电材料上方的导电材料，但是在其它方向上没有实质的导电性。此外，单向导电材料可以在垂直于其形成的表面的方向或沿着或跨平面的方向上导电，但在其它方向上不具有实质的导电性。最后，单向导电材料可能具有倾向于减少金属扩散，减少电子迁移，提供粘附或粘结和/或用作蚀刻停止的性质。

5. 发明授权

US5081051A Method for conditioning the surface of a polishing pad 失效
标题翻译：调整抛光垫表面的方法
公开(公告)号：US5081051A
公开(公告)日：1992-01-14
申请号：US581292
申请日：1990-09-12
申请人： Wayne A. Mattingly , Seiichi Morimoto , Spencer E. Preston
发明人： Wayne A. Mattingly , Seiichi Morimoto , Spencer E. Preston
IPC分类号： B24B53/007 , B24B53/017
CPC分类号： B24B53/017
摘要： An improved method for conditioning the surface of a pad for polishing a dielectric layer formed on a semiconductor substrate is disclosed. In one embodiment, the serrated edge of an elongated blade member is first placed in radial contact with the surface of the polishing pad. The table and the pad are then rotated relative to the blade member. At the same time, the blade member is pressed downwardly against the pad surface such that the serrated edge cuts a plurality of substantially circumferential grooves into the pad surface. These grooves are dimensioned so as to facilitate the polishing process by creating point contacts which increases the pad area and allows more slurry to applied to the substrate per unit area. Depending on the type of pad employed, the number of teeth per inch on the serrated edge, the type of slurry used, etc., the downward force applied to the blade member in the rotational speed of the table are optimized to obtain the resultant polishing rate and uniformity desired.
摘要翻译：公开了一种用于调节用于抛光形成在半导体衬底上的电介质层的焊盘表面的改进方法。在一个实施例中，细长叶片构件的锯齿状边缘首先被放置成与抛光垫的表面径向接触。然后桌子和垫子相对于叶片构件旋转。同时，刀片构件被向下压靠在衬垫表面上，使得锯齿形边缘将多个基本上周向的凹槽切割成垫表面。这些槽的尺寸被设计成便于通过产生点接触来促进抛光过程，这增加了焊盘面积，并允许更多的浆料被施加到每单位面积的衬底上。根据所使用的垫的类型，锯齿形边缘上每英寸的齿数，所使用的浆料的类型等，优化了以工作台转速施加到叶片构件的向下的力，以获得所得到的抛光所需的速率和均匀性。

6. 发明授权

US08334184B2 Polish to remove topography in sacrificial gate layer prior to gate patterning 有权
标题翻译：用于在栅极图案化之前去除牺牲栅极层中的形貌
公开(公告)号：US08334184B2
公开(公告)日：2012-12-18
申请号：US12646450
申请日：2009-12-23
申请人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
发明人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
IPC分类号： H01L21/336 , H01L21/70
CPC分类号： H01L29/66795 , H01L21/28123 , H01L29/66545 , H01L29/785
摘要： Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.
摘要翻译：公开了用于制造FinFET晶体管（例如，双栅极，三极管等）的技术。牺牲栅极材料（例如多晶硅或其他合适的材料）沉积在鳍结构上，并且在栅极图案化之前抛光以去除牺牲栅极材料层中的形貌。平坦的，无地形的表面（例如，取决于形成的最小特征的尺寸，平均度为50nm或更好）使得后续的栅极图案化和牺牲栅极材料在FinFET工艺流程中打开（经由抛光）。使用本文描述的技术可以以结构方式表现。例如，当栅极在翅片上行进时，顶栅表面相对平坦（例如，平均度为5至50nm，取决于最小栅极高度或其他最小特征尺寸）。此外，栅极线的自顶向下检查通常将显示没有或最小的线边缘偏离或扰动，因为线在翅片上延伸。

7. 发明授权

US5672095A Elimination of pad conditioning in a chemical mechanical polishing process 失效
标题翻译：在化学机械抛光过程中消除垫调节
公开(公告)号：US5672095A
公开(公告)日：1997-09-30
申请号：US536570
申请日：1995-09-29
申请人： Seiichi Morimoto , Ebrahim Andideh
发明人： Seiichi Morimoto , Ebrahim Andideh
IPC分类号： B24B37/04 , B24B53/00 , B24B1/00
CPC分类号： B24B37/042
摘要： A method and apparatus for polishing a film formed over a semiconductor substrate. The substrate is pressed up against an abrasive pad so that the film contacts the pad. The pad has a diameter which is less than approximately two times a diameter of the substrate. While pressure is applied to the back of the substrate, the pad is rotated with respect to the wafer and an abrasive ceria slurry is introduced onto the pad to polish the film.
摘要翻译：一种用于抛光形成在半导体衬底上的膜的方法和设备。将衬底压靠在研磨垫上，使得膜接触衬垫。焊盘的直径小于基板直径的大约两倍。当压力施加到基板的背面时，垫相对于晶片旋转，并且磨料二氧化铈浆料被引入到垫上以抛光该膜。

8. 发明授权

US6081272A Merging dummy structure representations for improved distribution of artifacts in a semiconductor layer 失效
标题翻译：合并虚拟结构表示以改善半导体层中伪影的分布
公开(公告)号：US6081272A
公开(公告)日：2000-06-27
申请号：US941599
申请日：1997-09-30
申请人： Seiichi Morimoto , Timothy L. Deeter
发明人： Seiichi Morimoto , Timothy L. Deeter
IPC分类号： G06F15/00 , G06F17/50 , H01L21/3105
CPC分类号： G06F17/5068 , H01L21/31053
摘要： A method for optimally sizing dummy structures in an integrated circuit design is disclosed. Adjacent dummy structures are merged to provide a composite merged dummy structure. Each side of a first dummy structure representation is expanded in a lateral direction by a predetermined distance such that the first dummy structure representation merges with an adjacent second dummy structure representation forming the composite merged dummy structure. The composite merged dummy structure is then examined to determine if it exceeds a predetermined size. If the composite merged dummy structure exceeds the predetermined size, then the composite merged dummy structure is contracted to fit within predetermined perimeters.
摘要翻译：公开了一种用于在集成电路设计中优化虚拟结构的尺寸的方法。相邻的虚拟结构被合并以提供复合合并虚拟结构。第一虚拟结构表示的每一侧在横向方向上扩展预定距离，使得第一虚拟结构表示与形成复合合并虚拟结构的相邻第二虚拟结构表示合并。然后检查复合合并虚拟结构以确定其是否超过预定大小。如果复合合并虚拟结构超过预定尺寸，则复合合并虚拟结构收缩以适应预定的周长。

9. 发明授权

US5911111A Polysilicon polish for patterning improvement 失效
标题翻译：多晶硅抛光剂用于图案改进
公开(公告)号：US5911111A
公开(公告)日：1999-06-08
申请号：US944041
申请日：1997-09-02
申请人： Mark T. Bohr , Lawrence N. Brigham , Peter K. Moon , Seiichi Morimoto
发明人： Mark T. Bohr , Lawrence N. Brigham , Peter K. Moon , Seiichi Morimoto
IPC分类号： H01L21/28 , H01L21/321 , H01L21/44
CPC分类号： H01L21/3212 , H01L21/28123
摘要： A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.
摘要翻译：在制造高性能金属氧化物半导体（MOS）器件中使用标准图案化技术的多晶硅栅极图案化改进的抛光工艺。在沉积之后和在多晶硅层的图案化之前添加短硅抛光步骤减少了通常与多晶硅相关的非平面性。多晶硅抛光消除由多晶硅的晶粒结构引起的多晶硅层中的表面粗糙度以及由于隔离和衬底区域的底部形貌的复制所引起的表面粗糙度。所描述的用于去除两种类型的表面粗糙度的方法使多晶硅层平坦化，而不增加已经与高性能MOS器件的制造相关联的缺陷水平。

10. 发明申请

US20110147812A1 POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE PATTERNING 有权
标题翻译：在移动栅栏之前，移除邻近门控层的波形
公开(公告)号：US20110147812A1
公开(公告)日：2011-06-23
申请号：US12646450
申请日：2009-12-23
申请人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
发明人： Joseph M. Steigerwald , Uday Shah , Seiichi Morimoto , Nancy Zelick
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L21/28123 , H01L29/66545 , H01L29/785
摘要： Techniques are disclosed for fabricating FinFET transistors (e.g., double-gate, trigate, etc). A sacrificial gate material (such as polysilicon or other suitable material) is deposited on fin structure, and polished to remove topography in the sacrificial gate material layer prior to gate patterning. A flat, topography-free surface (e.g., flatness of 50 nm or better, depending on size of minimum feature being formed) enables subsequent gate patterning and sacrificial gate material opening (via polishing) in a FinFET process flow. Use of the techniques described herein may manifest in structural ways. For instance, a top gate surface is relatively flat (e.g., flatness of 5 to 50 nm, depending on minimum gate height or other minimum feature size) as the gate travels over the fin. Also, a top down inspection of gate lines will generally show no or minimal line edge deviation or perturbation as the line runs over a fin.
摘要翻译：公开了用于制造FinFET晶体管（例如，双栅极，三极管等）的技术。牺牲栅极材料（例如多晶硅或其他合适的材料）沉积在鳍结构上，并且在栅极图案化之前抛光以去除牺牲栅极材料层中的形貌。平坦的，无地形的表面（例如，取决于形成的最小特征的尺寸，平均度为50nm或更好）使得后续的栅极图案化和牺牲栅极材料在FinFET工艺流程中打开（经由抛光）。使用本文描述的技术可以以结构方式表现。例如，当栅极在翅片上行进时，顶栅表面相对平坦（例如，平均度为5至50nm，取决于最小栅极高度或其他最小特征尺寸）。此外，栅极线的自顶向下检查通常将显示没有或最小的线边缘偏离或扰动，因为线在翅片上延伸。

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