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1. 发明授权

US5557538A MPEG decoder 失效
标题翻译： MPEG解码器
公开(公告)号：US5557538A
公开(公告)日：1996-09-17
申请号：US245469
申请日：1994-05-18
申请人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill , Ricardo Jaliff , Ram Ofir , Alon Boner , Oded Ilan , Eliezer Hassut
发明人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill , Ricardo Jaliff , Ram Ofir , Alon Boner , Oded Ilan , Eliezer Hassut
IPC分类号： G06T9/00 , H04N5/44 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/4143 , H04N21/434 , H04N11/02 , H04N7/12 , H04N11/04
CPC分类号： H04N5/4401 , H04N19/42 , H04N19/61 , H04N21/426 , H04N21/4305 , H04N21/4402
摘要： An MPEG decoder which distributes the processing load to a plurality of processors and units including an external memory and a bus interface unit, a de-multiplexing data processor, an image data processor, an inverse transform and reconstruction processor, and a prediction calculation unit. A video post-processing unit generates video data, and a serial port unit provides an output for audio data.
摘要翻译：将处理负荷分配给包括外部存储器和总线接口单元的多个处理器以及解复用数据处理器，图像数据处理器，逆变换和重建处理器以及预测计算单元的MPEG解码器。视频后处理单元生成视频数据，并且串行端口单元提供用于音频数据的输出。

2. 发明授权

US5712665A Dynamic random access memory for MPEG decoding 失效
标题翻译：用于MPEG解码的动态随机存取存储器
公开(公告)号：US5712665A
公开(公告)日：1998-01-27
申请号：US661135
申请日：1996-06-10
申请人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill
发明人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill
IPC分类号： H04N7/26 , H04N7/50 , G09G5/00
CPC分类号： H04N19/423 , H04N19/61
摘要： A dynamic random access memory (DRAM) for use in MPEG decoding includes d devices each having r rows and c columns with b bits per cell and p samples, where b*d is divisible by 8 and r*c is larger than a sum of upstream buffers in bytes and either 2 or 3 times 1.5*1*p divided by (b*d/8). First and second reference picture components are organized first along a depth axis (d) and then along rows (r) with complete lines of a component occupying the same row with the memory region occupied by each component being rectangular and third reference signal components are organized first along a depth axis and then along rows and occupying a largest possible part of each row in multiples of 8*(8/(b*d)).
摘要翻译：用于MPEG解码的动态随机存取存储器（DRAM）包括d个装置，每个装置具有r行和c列，每个单元b位和p个样本，其中b * d可被8整除，r * c大于上游缓冲区为字节，2或3倍1.5 * 1 * p除以（b * d / 8）。第一和第二参考图像分量首先沿着深度轴（d）组织，然后沿着行（r），其中占据同一行的分量的完整行与每个分量占据的存储区域是矩形的，并且第三参考信号分量被组织首先沿着深度轴，然后沿着行，并以8 *（8 /（b * d））的倍数占据每行的最大可能部分。

3. 发明授权

US5623314A MPEG decoder memory data storage and transfer 失效
标题翻译： MPEG解码器存储数据存储和传输
公开(公告)号：US5623314A
公开(公告)日：1997-04-22
申请号：US245740
申请日：1994-05-18
申请人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill
发明人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50
CPC分类号： H04N19/423 , H04N19/61
摘要： Data transfer and timing in an external DRAM memory of an MPEG decoder utilizes a repetitive pattern for synchronous writing and reading of data and data refresh including a sequence header at the beginning of a picture, a macroblock header for each of the macroblocks of a picture, and a plurality of repetitions of block decoding after each macroblock header decode.
摘要翻译： MPEG解码器的外部DRAM存储器中的数据传送和定时利用重复模式，用于同步写入和读取数据和数据刷新，包括图像开始处的序列头，用于图像的每个宏块的宏块头，以及在每个宏块头部解码之后的多个重复的块解码。

4. 发明授权

US5903311A Run level pair buffering for fast variable length decoder circuit 失效
标题翻译：用于快速可变长度解码器电路的运行电平对缓冲
公开(公告)号：US5903311A
公开(公告)日：1999-05-11
申请号：US866701
申请日：1997-05-30
申请人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
发明人： Taner Ozcelik , Shirish C. Gadre , Moshe Bublil , Sabyasachi Dutta , Subroto Bose
IPC分类号： G06T9/00 , H03M7/40 , H04N7/26 , H04N7/50 , A04N7/30
CPC分类号： H03M7/40 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61 , H04N19/13 , H04N19/91
摘要： A decoding circuit for decoding (or decompressing) compressed video data includes an RL circuit, such as MPEG encoded video data. The RL circuit includes a buffer memory for storing run-level pairs during the decoding process. Because the buffer memory in the RL circuit can store ran-level pairs, Huffman-decoding and header decoding, performed by a variable length decoding (VLD) circuit, is decoupled from inverse discrete transform decoding, performed by an IDCT circuit. This decoupling speeds up the decoding pipeline by allowing more continuous operation by both the VLD and IDCT circuits.
摘要翻译：用于解码（或解压缩）压缩视频数据的解码电路包括诸如MPEG编码视频数据的RL电路。 RL电路包括用于在解码过程期间存储运行电平对的缓冲存储器。由于RL电路中的缓冲存储器可以存储运行电平对，由可变长度解码（VLD）电路执行的霍夫曼解码和报头解码与由IDCT电路执行的反离散变换解码分离。这种去耦通过允许VLD和IDCT电路的更连续的操作来加速解码流水线。

5. 发明授权

US06934338B1 Variable length decoder for decoding digitally encoded video signals 失效
标题翻译：用于解码数字编码视频信号的可变长度解码器
公开(公告)号：US06934338B1
公开(公告)日：2005-08-23
申请号：US10662645
申请日：2003-09-15
申请人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
发明人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
IPC分类号： G06T9/00 , H04N7/26 , H04N7/30 , H04N7/50 , H04N7/12
CPC分类号： H04N19/00 , H04N19/42 , H04N19/60 , H04N19/70 , H04N19/90 , H04N19/91
摘要： A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.
摘要翻译：用于解码MPEG-1和-2语法兼容视频比特流的可变长度解码器（VLD）。 VLD包括用于使用新颖的指令集来控制MPEG解码处理的微定序器和VLD命令解码/执行单元。指令集包括用于解码视频数据的一组命令和一组流控制指令。提供一个旋转器/桶形移位器，用于从VLD可用的视频比特流和可变长度表解码器中使用MPEG标准可变长度码（VLC）表来进行可变长度解码，从而使预定数量的编码比特。可变长度表解码器在所有VLC表中共享前缀模式匹配方案，并将可变长度代码组织成一系列子表。每个子表都对应于唯一前缀模式之一。通过识别视频数据位流中的引导图案并且并行地访问与该引导图案相对应的子表，来对可变长度代码进行解码。运行长度和幅度级DCT系数符号以压缩形式存储，并根据需要由逆变换单元进行解码。运动矢量也被存储直到运动补偿单元需要。

6. 发明授权

US06704361B2 Variable length decoder for decoding digitally encoded video signals 失效
标题翻译：用于解码数字编码视频信号的可变长度解码器
公开(公告)号：US06704361B2
公开(公告)日：2004-03-09
申请号：US09280437
申请日：1999-03-29
申请人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
发明人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , John Hong , Taner Ozcelik
IPC分类号： H04N712
CPC分类号： H04N19/00 , H04N19/13 , H04N19/42 , H04N19/60 , H04N19/61 , H04N19/70 , H04N19/90 , H04N19/91
摘要： A variable length decoder (VLD) for decoding MPEG-1 and -2 syntax compliant video bit streams. The VLD includes a micro-sequencer and VLD command decode/execution unit for controlling the MPEG decoding process using a novel instruction set. The instruction set includes a set of commands for decoding the video data and a set of flow control instructions. A rotator/barrel shifter is provided for making a predetermined number of encoded bits from the video bit stream available to the VLD and a variable length table decoder for variable length decoding using the MPEG standard variable length code (VLC) tables. The variable length table decoder shares a prefix pattern matching scheme across all of the VLC tables and organizes the variable length codes into a series of subtables. Each subtable corresponds to one of the unique prefix patterns. Variable length codes are decoded by identifying a leading pattern in the video data bit stream and, in parallel, accessing the subtable corresponding to that leading pattern. Run-length and amplitude level DCT coefficient symbols are stored in compressed form, and decoded as needed by an inverse transform unit. Motion vectors are also stored until needed by a motion compensation unit.
摘要翻译：用于解码MPEG-1和-2语法兼容视频比特流的可变长度解码器（VLD）。 VLD包括用于使用新颖的指令集来控制MPEG解码处理的微定序器和VLD命令解码/执行单元。指令集包括用于解码视频数据的一组命令和一组流控制指令。提供一个旋转器/桶形移位器，用于从VLD可用的视频比特流和可变长度表解码器中使用MPEG标准可变长度码（VLC）表来进行可变长度解码，从而使预定数量的编码比特。可变长度表解码器在所有VLC表中共享前缀模式匹配方案，并将可变长度代码组织成一系列子表。每个子表都对应于唯一前缀模式之一。通过识别视频数据位流中的引导图案并且并行地访问与该引导图案相对应的子表，来对可变长度代码进行解码。运行长度和幅度级DCT系数符号以压缩形式存储，并根据需要由逆变换单元进行解码。运动矢量也被存储直到运动补偿单元需要。

7. 发明授权

US6012137A Special purpose processor for digital audio/video decoding 失效
标题翻译：专用处理器，用于数字音频/视频解码
公开(公告)号：US6012137A
公开(公告)日：2000-01-04
申请号：US865749
申请日：1997-05-30
申请人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , Taner Ozcelik
发明人： Moshe Bublil , Subroto Bose , Shirish C. Gadre , Taner Ozcelik
IPC分类号： G06F9/308 , G06F9/312 , G06F9/32 , G06F9/38 , G06F15/78 , G06F15/76
CPC分类号： G06F9/30018 , G06F15/7832 , G06F9/30043 , G06F9/30101 , G06F9/30167 , G06F9/322 , G06F9/3824 , G06F9/3836
摘要： A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives. To further reduce instruction latency, if an instruction makes use of the contents of a register that is in the process of being written by an immediately preceding instruction, the RISC CPU "bypasses" the register file, using previous results directly in a subsequent instruction. For the purposes of control and debugging, the PC can be read or written by an external host, and instructions can be loaded directly from the host. Also, pages of instructions can be loaded to or from the instruction memory to allow for an unlimited virtual instruction memory space.
摘要翻译：用于控制数字音频/视频解码的特殊目的简化指令集中央处理单元（RISC CPU）。指令集包括流量控制指令，其包含用于跳过少量指令的立即值以及用于较大跳跃的其他指令。此外，指令以流线型方式从ASIC的视频解码器获取数据，使用硬编码到RISC CPU中的视频解码器地址。进一步的指令执行用作状态/状态标志的寄存器的各个位的操作。 RISC CPU包括监视功能，用于监视从其他功能单元或从存储器向RISC CPU传送数据，以便RISC CPU可以执行指令，同时从存储器或其他功能单元传输数据仍在等待，除非该数据是必要的对于程序执行，在这种情况下，程序执行停止，直到数据到达。为了进一步减少指令等待时间，如果指令利用正在前一条指令写入的寄存器的内容，RISC CPU将“暂停”寄存器文件，直接在后续指令中使用先前的结果。为了进行控制和调试，PC可以由外部主机读取或写入，并且可以直接从主机加载指令。此外，可以将指令页加载到指令存储器或从指令存储器加载，以允许无限制的虚拟指令存储器空间。

8. 发明授权

US5916312A ASIC having flexible host CPU interface for ASIC adaptable for multiple processor family members 失效
标题翻译： ASIC具有灵活的主机CPU接口，适用于多个处理器家庭成员的ASIC
公开(公告)号：US5916312A
公开(公告)日：1999-06-29
申请号：US851695
申请日：1997-05-06
申请人： Quang C. Phung , Moshe Bublil
发明人： Quang C. Phung , Moshe Bublil
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： A CPU interface having an 8-bit mode in which the interface is capable of interfacing with a host CPU having 8-bit data bus, and a 16-bit mode in which the interface is capable of interfacing with a host CPU having a 16-bit data bus. The host CPU interface is further capable of switching between its 8-bit and 16-bit modes in real time in response to a 16-bit host CPU entering sections of 8-bit or 16-bit software. The interface also has "direct" and "indirect" addressing modes, so that the interface can send or receive time-multiplexed data, and receive address information on a single bus ("indirect" mode) or send or receive data, and receive address information in parallel on separate buses ("direct" mode).
摘要翻译：具有8位模式的CPU接口，其中接口能够与具有8位数据总线的主机CPU接口，以及16位模式，其中接口能够与具有16位数据总线的主机CPU进行接口，位数据总线。主机CPU接口还能够实时切换其8位和16位模式，以响应16位主机CPU进入8位或16位软件的部分。该接口还具有“直接”和“间接”寻址模式，因此接口可以发送或接收时分多路复用数据，并在单个总线（“间接”模式）上接收地址信息或发送或接收数据，并接收地址在单独的总线上并行提供信息（“直接”模式）。

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