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1. 发明授权

US5557538A MPEG decoder 失效
标题翻译： MPEG解码器
公开(公告)号：US5557538A
公开(公告)日：1996-09-17
申请号：US245469
申请日：1994-05-18
申请人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill , Ricardo Jaliff , Ram Ofir , Alon Boner , Oded Ilan , Eliezer Hassut
发明人： Refael Retter , Moshe Bublil , Gad Shavit , Aharon Gill , Ricardo Jaliff , Ram Ofir , Alon Boner , Oded Ilan , Eliezer Hassut
IPC分类号： G06T9/00 , H04N5/44 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/4143 , H04N21/434 , H04N11/02 , H04N7/12 , H04N11/04
CPC分类号： H04N5/4401 , H04N19/42 , H04N19/61 , H04N21/426 , H04N21/4305 , H04N21/4402
摘要： An MPEG decoder which distributes the processing load to a plurality of processors and units including an external memory and a bus interface unit, a de-multiplexing data processor, an image data processor, an inverse transform and reconstruction processor, and a prediction calculation unit. A video post-processing unit generates video data, and a serial port unit provides an output for audio data.
摘要翻译：将处理负荷分配给包括外部存储器和总线接口单元的多个处理器以及解复用数据处理器，图像数据处理器，逆变换和重建处理器以及预测计算单元的MPEG解码器。视频后处理单元生成视频数据，并且串行端口单元提供用于音频数据的输出。

2. 发明申请

US20080186319A1 Dynamically activated frame buffer 审中-公开
标题翻译：动态启动帧缓冲区
公开(公告)号：US20080186319A1
公开(公告)日：2008-08-07
申请号：US11702215
申请日：2007-02-05
申请人： Alon Boner
发明人： Alon Boner
IPC分类号： G09G5/36
CPC分类号： G09G5/393 , G09G5/001 , G09G2330/021 , G09G2340/02
摘要： Methods and systems for storing or not storing images in a frame buffer during the provision of images to a screen. In one embodiment, the selective usage of the frame buffer may lead to a reduction in power consumption.
摘要翻译：在向屏幕提供图像期间存储或不将图像存储在帧缓冲器中的方法和系统。在一个实施例中，帧缓冲器的选择性使用可导致功耗的降低。

3. 发明授权

US06950977B2 Mechanism for turbo decoding when CRC for partial blocks is provided 失效
标题翻译：提供用于部分块的CRC的turbo解码机制
公开(公告)号：US06950977B2
公开(公告)日：2005-09-27
申请号：US10097609
申请日：2002-03-15
申请人： Yoav Lavi , Alon Boner
发明人： Yoav Lavi , Alon Boner
IPC分类号： H03M13/09 , H03M13/27 , H03M13/29 , H03M13/03
CPC分类号： H03M13/2975 , H03M13/09
摘要： A system and method for improving error detection and correction for transmitted data. An iterative error detection method is used to determine a relative likelihood that decoded data is an accurate representation of the original data. An independent error correction unit operates on the decoded data and a result from the independent error correction unit is injected into the iterative error detection method to improve the reliability of the error detection method.
摘要翻译：一种用于改进发送数据的错误检测和校正的系统和方法。迭代误差检测方法用于确定解码数据是原始数据的准确表示的相对似然性。独立的纠错单元对解码的数据进行操作，将独立误差校正单元的结果注入到迭代误差检测方法中，以提高误差检测方法的可靠性。

4. 发明授权

US06625763B1 Block interleaver and de-interleaver with buffer to reduce power consumption 失效
标题翻译：使用缓冲区块交织器和解交织器以降低功耗
公开(公告)号：US06625763B1
公开(公告)日：2003-09-23
申请号：US09610302
申请日：2000-07-05
申请人： Alon Boner
发明人： Alon Boner
IPC分类号： G06F1100
CPC分类号： H04L1/0071 , H03M13/2703
摘要： A block interleaver is provided using a relatively small register file and a larger random access memory (RAM). In one embodiment, the size of the RAM is larger than the size of the register file by at least one order of magnitude. As a result, the register file consumes significantly less power than the RAM for similar operations. The register file receives a stream of sequential data values and stores the data values in a column order. The data values are then read from the register file in a row order. The data values read from the register file in a row order are then written to the RAM in a row order. The data values are then read from the RAM in a row order, thereby creating an interleaved data stream. In a particular embodiment, the data values are written to the RAM in a staggered row order and read from the RAM in a sequential row order. All accesses to the RAM are performed using the full width of the RAM, such that no unnecessary power is used to access the RAM. The register file consumes significantly less power than the RAM, thereby providing an overall power savings for the interleaving process. In different embodiments, the register file can be a single-port device or a dual-port device. A similar block de-interleaver is provided in another embodiment.
摘要翻译：使用相对小的寄存器文件和较大的随机存取存储器（RAM）来提供块交织器。在一个实施例中，RAM的大小比寄存器文件的大小大至少一个数量级。因此，与类似操作相比，寄存器文件的功耗明显低于RAM。寄存器文件接收顺序数据值流并以列顺序存储数据值。然后以一行的顺序从寄存器文件中读取数据值。然后以行顺序从寄存器文件读取的数据值按行顺序写入RAM。然后，按照行顺序从RAM读取数据值，从而创建交错的数据流。在特定实施例中，数据值以交错的行顺序写入RAM，并以顺序行顺序从RAM读取。使用RAM的全部宽度来执行对RAM的所有访问，使得不需要不必要的电力来访问RAM。寄存器文件消耗的功率明显低于RAM，从而为交错处理提供了总体功耗。在不同的实施例中，寄存器文件可以是单端口设备或双端口设备。在另一个实施例中提供了类似的块去交织器。

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