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1. 发明授权

US10522204B1 Memory signal phase difference calibration circuit and method 有权
公开(公告)号：US10522204B1
公开(公告)日：2019-12-31
申请号：US16183348
申请日：2018-11-07
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Chun-Chi Yu , Fu-Chin Tsai , Shih-Han Lin , Chih-Wei Chang , Gerchih Chou
IPC分类号： G11C7/22 , G06F3/06
摘要： A memory signal phase difference calibration circuit includes: a clock generator providing clocks allowing a physical layer (PHY) circuit of DDR SDRAM to generate a data input/output signal (DQ) and a data strobe signal (DQS) for accessing a storage circuit; a calibration control circuit outputting a phase control signal according to an adjustment range to adjust the phase of a target signal (DQ or DQS), and outputting a calibration control signal; an access control circuit reading storage data representing predetermined data from the storage circuit according to the calibration control signal; a comparison circuit comparing the predetermined data with the storage data to output a result allowing the calibration control circuit to alter the adjustment range accordingly; and a phase controller outputting a clock control signal according to the phase control signal to set the phase of a target clock used for the PHY circuit generating the target signal.

2. 发明授权

US12088359B2 Receiver of communication system and eye diagram measuring method 有权
公开(公告)号：US12088359B2
公开(公告)日：2024-09-10
申请号：US17938050
申请日：2022-10-05
申请人： Realtek Semiconductor Corporation
发明人： Shih-Chang Chen , Chih-Wei Chang , Chun-Chi Yu
IPC分类号： H04B17/345
CPC分类号： H04B17/345
摘要： An eye diagram measuring method includes: sampling a compensated input signal according to a reference voltage and a reference clock to obtain a first sampling result; and sampling a to-be-compensated input signal according to a scan voltage and a scan clock to obtain a second sampling result, including: (b1) storing a minimum phase and a voltage level which render the first sampling result identical to the second sampling result; (b2) increasing the voltage level and repeating operation (b1); (b3) decreasing the voltage level and repeating operation (b1); (b4) storing a maximum phase and the voltage level which render the first sampling result identical to the second sampling result; (b5) increasing the voltage level and repeating operation (b4); and (b6) decreasing the voltage level and repeating operation (b4). Voltage levels, maximum phases and minimum phases that are stored are for adjusting the reference voltage and the reference clock.

3. 发明授权

US10998061B1 Memory system and memory access interface device thereof 有权
公开(公告)号：US10998061B1
公开(公告)日：2021-05-04
申请号：US16874958
申请日：2020-05-15
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Fu-Chin Tsai , Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou
IPC分类号： G11C7/00 , G11C16/32 , G11C16/26 , G11C16/04
摘要： The present disclosure discloses a memory access interface device. A clock generation circuit generates a command reference clock signal. Each of the access signal transmission circuits adjusts a phase and a duty cycle of one of access signals from a memory access controller according to the command reference clock signal to generate one of output access signal including an output external read enable signal to activate a memory device and an output internal read enable signal. The data reading circuit samples a data signal from the activated memory device according to a sampling signal to generate and transmit a read data signal to the memory access controller. The multiplexer generates the sampling signal according to the output internal read enable signal under a SDR mode and generates the sampling signal according to a data strobe signal from the activated memory device under a DDR mode.

4. 发明授权

US10643685B1 Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof 有权
公开(公告)号：US10643685B1
公开(公告)日：2020-05-05
申请号：US16177603
申请日：2018-11-01
申请人： Realtek Semiconductor Corporation
发明人： Chun-Chi Yu , Gerchih Chou , Chih-Wei Chang , Shen-Kuo Huang
IPC分类号： G11C8/18 , G11C11/4076 , G11C11/409
CPC分类号： G11C11/4076 , G11C11/409
摘要： The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.

5. 发明授权

US10269443B2 Memory device and test method of the same 有权
公开(公告)号：US10269443B2
公开(公告)日：2019-04-23
申请号：US15894844
申请日：2018-02-12
申请人： Realtek Semiconductor Corporation
发明人： Chun-Chi Yu , Chih-Wei Chang , Shen-Kuo Huang
IPC分类号： G11C29/00 , G11C29/02 , G11C11/4076 , G11C29/50 , G11C11/409 , G11C11/4063
摘要： A memory test method is provided that includes the steps outlined below. The memory controller performs data-writing and data-reading on a memory module. When a quantity of read data is incorrect, a data-strobe enable signal is calibrated to perform data reading. When there is one of less than one piece of negative edge data reading content, a sampling unit is triggered. When the quantity of read data increases, the condition that the data-strobe signal is not received is determined. When the quantity does not increase, the memory controller is inspected. When there is more than one piece of read data, the burst mode setting of the memory module is inspected. When the quantity is correct and the content is not correct, a transmission circuit setting and the sampling unit are inspected. When the quantity and the content are correct, the test flow is terminated.

6. 发明授权

US10056124B2 Memory control device for repeating data during a preamble signal or a postamble signal and memory control method 有权
公开(公告)号：US10056124B2
公开(公告)日：2018-08-21
申请号：US15378199
申请日：2016-12-14
申请人： Realtek Semiconductor Corporation
发明人： Chun-Chi Yu , Chih-Wei Chang , Shen-Kuo Huang , Gerchih Chou
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1027 , G11C7/222
摘要： A memory control device, which includes a signal generating circuit, a data writing circuit and a repeating circuit. The repeating circuit is coupled to the data writing circuit. The signal generating circuit is configured to generate a data strobe signal and send the data strobe signal to a memory. The data strobe signal comprises a preamble signal. The data writing circuit is configured to write a series of data to the memory according to the data strobe signal. The repeating circuit is configured to repeat a first data of the series of data in a period of the preamble signal.

7. 发明申请

US20150049562A1 MEMORY CONTROL CIRCUIT AND METHOD OF CONTROLLING DATA READING PROCESS OF MEMORY MODULE 有权
标题翻译：存储器控制电路和控制存储器模块的数据读取过程的方法
公开(公告)号：US20150049562A1
公开(公告)日：2015-02-19
申请号：US14326869
申请日：2014-07-09
申请人： Realtek Semiconductor Corporation
发明人： Chun-Chi Yu , Chih-Wei Chang , Shen-Kuo Huang
IPC分类号： G11C11/4091 , G11C11/4076
CPC分类号： G11C11/4076 , G06F13/1689 , G11C7/1057 , G11C7/1066 , G11C11/4091
摘要： This invention discloses a memory control circuit and method of controlling a data reading process of a memory module. In the data reading process, the memory module transmits a data signal and a data strobe signal used to recover the data signal. The data strobe signal includes a preamble part. The method includes steps of: controlling an impedance matching circuit of the memory module so that the data strobe signal is kept at a fixed level before the preamble part; generating a clock; generating an enabling signal according to the clock; sampling the data strobe signal according to the enabling signal to generate a sampled result; adjusting an enabling time of the enabling signal according to the sampled result; and starting a data recovering process for the data signal according to the enabling signal.
摘要翻译：本发明公开了一种存储器控制电路和控制存储器模块的数据读取过程的方法。在数据读取处理中，存储器模块发送用于恢复数据信号的数据信号和数据选通信号。数据选通信号包括前导码部分。该方法包括以下步骤：控制存储器模块的阻抗匹配电路，使得数据选通信号在前同步码部分之前保持在固定电平; 产生时钟; 根据时钟产生使能信号; 根据使能信号对数据选通信号进行采样，生成采样结果; 根据采样结果调整使能信号的使能时间; 并根据使能信号开始数据信号的数据恢复处理。

8. 发明授权

US11823770B1 Memory system and memory access interface device thereof 有权
公开(公告)号：US11823770B1
公开(公告)日：2023-11-21
申请号：US17735142
申请日：2022-05-03
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Ger-Chih Chou , Chih-Wei Chang , Li-Jun Gu , Chun-Chi Yu , Fu-Chin Tsai
IPC分类号： G11C7/22 , G11C8/18 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1066 , G11C7/1093 , G11C8/18
摘要： The present disclosure discloses a memory access interface device. A data processing circuit receives a data signal including 2M pieces of data from a memory device. A sampling clock generation circuit receives a data strobe signal from the memory device to generate a valid data strobe signal having P valid strobe pulses and further generate a sampling clock signal accordingly, in which P is larger than M. A sampling circuit samples the data signal according to the sampling clock signal to generate sampling results. A control circuit determines valid sampling results according to a time difference between the valid data strobe signal and the data signal and outputs valid data generated according to the valid sampling results as a read data signal to a memory access controller.

9. 发明授权

US11816352B2 Electronic device, data strobe gate signal generator circuit and data strobe gate signal generating method 有权
公开(公告)号：US11816352B2
公开(公告)日：2023-11-14
申请号：US17507864
申请日：2021-10-22
申请人： Realtek Semiconductor Corporation
发明人： Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou
IPC分类号： G06F3/06 , G06F1/06 , G11C11/4076 , H03K19/00 , H03K19/20
CPC分类号： G06F3/0655 , G06F1/06 , G06F3/0604 , G06F3/0673 , G11C11/4076 , H03K19/0005 , H03K19/20
摘要： A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.

10. 发明授权

US10698846B2 DDR SDRAM physical layer interface circuit and DDR SDRAM control device 有权
公开(公告)号：US10698846B2
公开(公告)日：2020-06-30
申请号：US16182680
申请日：2018-11-07
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Kuo-Wei Chi , Chun-Chi Yu , Chih-Wei Chang , Gerchih Chou , Shih-Chang Chen
IPC分类号： G06F13/16 , G11C7/22 , G06F3/06
摘要： Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.

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