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1. 发明授权

US06555296B2 Fine pitch wafer bumping process 有权
公开(公告)号：US06555296B2
公开(公告)日：2003-04-29
申请号：US09827080
申请日：2001-04-04
申请人： Raymond Jao , Eric Ko , Alex Yang
发明人： Raymond Jao , Eric Ko , Alex Yang
IPC分类号： H01L2160
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/05001 , H01L2224/05022 , H01L2224/05171 , H01L2224/05572 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/1146 , H01L2224/1147 , H01L2224/11474 , H01L2224/11502 , H01L2224/11849 , H01L2224/11906 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/00014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H05K3/3484 , H05K2203/043 , H05K2203/0568 , H05K2203/0577 , H01L2224/05644 , H01L2224/05647 , H01L2224/05684 , H01L2224/05099 , H01L2924/013
摘要： A fine pitch wafer bumping process comprises: providing a wafer that has a plurality of contact pads exposed by a passivation layer formed on the surface of the wafer, wherein an under bump metal (UBM) is formed respectively on each contact pad; on the surface of the wafer, forming a first mask film having a plurality of first openings that expose respectively the under bump metals (UBM); filling a first solder material respectively in the first openings; reflowing the first solder material into a plurality of solder posts; on the first mask film, forming a second mask film having a plurality of second openings that respectively expose the first openings; filling a second solder material respectively in the second openings; reflowing the second solder material and the first solder posts; removing the first and second mask films; and reflowing the first and second solder posts to form a plurality of bumps.

2. 发明授权

US06282094B1 Ball-grid array integrated circuit package with an embedded type of heat-dissipation structure and method of manufacturing the same 失效
标题翻译：球栅阵列集成电路封装具有嵌入式散热结构及其制造方法
公开(公告)号：US06282094B1
公开(公告)日：2001-08-28
申请号：US09545996
申请日：2000-04-10
申请人： Randy H. Y. Lo , Jeng Yuan Lai , Eric Ko , Tzong-Da Ho
发明人： Randy H. Y. Lo , Jeng Yuan Lai , Eric Ko , Tzong-Da Ho
IPC分类号： H05K720
CPC分类号： H01L23/3677 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L2224/05599 , H01L2224/32188 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , Y10T29/49149 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A BGA (Ball-Grid Array) IC package with an unembedded type of heat-dissipation structure is proposed. The unembedded type of heat-dissipation structure is characterized in that a plurality of thermally-conductive vias are formed in the substrate and extending from the die-attachment area to the back side of the substrate; and further, a plurality of thermally-conductive balls are bonded to the thermally-conductive vias on the back side of the substrate. Moreover, a thermally-conductive layer is formed over a thermally-conductive area on the back side of the substrate on which the thermally-conductive balls are mounted for the purpose of increasing the exposed area of the overall heat-dissipation structure to the atmosphere. This allows the IC-produced heat during operation to be conducted through the thermally-conductive vias, the thermally-conductive balls, and the thermally-conductive layer to be dissipated the atmosphere. The unembedded manner of integration requires no openings to be formed in the substrate that would otherwise allow ambient moisture to enter into the inside of the package body as in the case of the prior art, and also allows the heat-dissipation structure to be more easily integrated to the package configuration. Due to these benefits, the BGA IC package can be manufactured through a more simplified and cost-effective process, while nevertheless providing a high heat-dissipation efficiency.
摘要翻译：提出了一种具有非嵌入式散热结构的BGA（球栅阵列）IC封装。未嵌入式的散热结构的特征在于，在基板中形成多个导热通孔，并且从管芯附着区域延伸到基板的背面; 此外，多个导热球接合到基板的背面上的导热通孔。此外，为了增加整个散热结构对大气的暴露面积，在其上安装有导热球的基板的背面上的导热区域上形成导热层。这允许在操作期间产生的IC产生的热量通过导热通孔，导热球和导热层传导以消散大气。未嵌入的集成方式不需要在基板中形成开口，否则将使现有技术的情况下环境湿气进入包装体的内部，并且还允许散热结构更容易集成到包配置。由于这些优点，BGA IC封装可以通过更简化和成本有效的工艺制造，同时仍然提供高散热效率。

3. 发明授权

US06246111B1 Universal lead frame type of quad flat non-lead package of semiconductor 有权
标题翻译：通用引线框架型四边形非导线封装半导体
公开(公告)号：US06246111B1
公开(公告)日：2001-06-12
申请号：US09490726
申请日：2000-01-25
申请人： Chien-Ping Huang , Eric Ko
发明人： Chien-Ping Huang , Eric Ko
IPC分类号： H01L23495
CPC分类号： H01L24/49 , H01L21/565 , H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49112 , H01L2224/49171 , H01L2924/01013 , H01L2924/01079 , H01L2924/10162 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An universal lead frame type of Quad Flat Non-Lead package of semiconductor comprises a chip, a plurality of leads, a heat sink, and a molding compound. The leads are disposed at the periphery of the chip. The chip has its back surface bonded to the top surface of the heat sink, and the periphery of the top surface of the heat sink has a plurality of projections. The bonding portion at the periphery on the bottom surface of the heat sink is bonded to the top surface of the leads. The protruded portion at the center of the bottom surface of the heat sink is disposed in the opening region such that the bottom surface of the heat sink and the bottom surface of the leads are coplaner. The bonding pads of the chip are electrically connected to the top surface of the leads by a plurality of bonding wires. The molding compound encapsulates the chip, the heat sink, the top surface of the leads, and the bonding wires while exposes the protruded portion of the heat sink.
摘要翻译：四通道非导体半导体封装的通用引线框架包括芯片，多个引线，散热器和模制化合物。引线设置在芯片的外围。芯片的后表面与散热器的顶面接合，散热片顶面的周边具有多个突起。散热器底面周边的接合部分接合到引线的顶表面。在散热器的底面的中心的突出部分设置在开口区域中，使得散热器的底表面和引线的底表面平行。芯片的接合焊盘通过多个接合线电连接到引线的顶表面。模制化合物封装芯片，散热器，引线的顶表面和接合线，同时暴露散热器的突出部分。

4. 发明授权

US06281578B1 Multi-chip module package structure 失效
标题翻译：多芯片模块封装结构
公开(公告)号：US06281578B1
公开(公告)日：2001-08-28
申请号：US09638989
申请日：2000-08-15
申请人： Randy H. Y. Lo , Chi-Chuan Wu , Han-Ping Pu , Eric Ko
发明人： Randy H. Y. Lo , Chi-Chuan Wu , Han-Ping Pu , Eric Ko
IPC分类号： H01L2334
CPC分类号： H01L23/49531 , H01L23/49575 , H01L23/49861 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/06136 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/4824 , H01L2224/48247 , H01L2224/4911 , H01L2224/73215 , H01L2224/73265 , H01L2924/01013 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A multi-chip module (MCM) integrated circuit package structure is proposed, which can be used to pack a plurality of semiconductor chips of different functions while nonetheless allowing the overall package size to be as small as some existing types of integrated circuit packages, such as the SO (Small Outline) and QFP (Quad Flat Package) types, so that it can be manufactured using the existing fabrication equipment. The proposed MCM integrated circuit package structure is characterized in the use of a substrate having a centrally-located opening, and at least one semiconductor chip is mounted on the front surface of the substrate and a semiconductor chip of a central-pad type having a plurality of centrally-located bonding pads is mounted on the back surface of the substrate with the centrally-located bonding pads being exposed through the opening. This arrangement allows the overall package size to be made very compact and also allows the wiring to the central-pad type semiconductor chip to be shortened.
摘要翻译：提出了一种多芯片模块（MCM）集成电路封装结构，可用于封装多个不同功能的半导体芯片，同时允许整体封装尺寸与现有类型的集成电路封装一样小，如作为SO（小外形）和QFP（四方扁平封装）类型，因此可以使用现有的制造设备制造。所提出的MCM集成电路封装结构的特征在于使用具有居中定位的开口的衬底，并且至少一个半导体芯片安装在衬底的前表面上，以及具有多个中心焊盘的半导体芯片中心定位的焊盘安装在基板的背面，中心位置的焊盘通过开口露出。这种布置使得整体封装尺寸变得非常紧凑，并且还允许缩短到中心焊盘型半导体芯片的布线。

5. 发明授权

US06265763B1 Multi-chip integrated circuit package structure for central pad chip 有权
标题翻译：多芯片集成电路封装结构，用于中心焊盘芯片
公开(公告)号：US06265763B1
公开(公告)日：2001-07-24
申请号：US09524944
申请日：2000-03-14
申请人： Jui-Meng Jao , Eric Ko , Vicky Liu
发明人： Jui-Meng Jao , Eric Ko , Vicky Liu
IPC分类号： H01L23495
CPC分类号： H01L24/32 , H01L23/4951 , H01L23/49513 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/73215 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01047 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A multi-chip IC package for central pad chips is proposed, which can be used to pack one peripheral-pad IC chip and at least one central-pad IC chip therein. The multi-chip IC package includes a specially-designed lead frame having a central die pad and a lead portion separated from the central die pad by a gap. The central-pad IC chip is partly attached to the lead portion of the lead frame and partly attached to the central die pad of the lead frame such that the central pads on the central-pad IC chip can be aligned with the gap of lead frame so as to allow bonding wires electrically connecting the central-pad IC chip with the lead portion of the lead frame to pass therethrough. The characterized package allows the bonding wires applied to the central-pad IC chip to be short in length so as to retain IC performance and save manufacture cost, making this multi-chip IC package structure more advantageous to use than the prior art.
摘要翻译：提出了一种用于中心焊盘芯片的多芯片IC封装，其可用于在其中封装一个外围焊盘IC芯片和至少一个中心焊盘IC芯片。多芯片IC封装包括一个特别设计的引线框架，其具有中央管芯焊盘和引线部分，该引线部分通过间隙与中心管芯焊盘分离。中心焊盘IC芯片部分地附接到引线框架的引线部分并且部分地附接到引线框架的中心管芯焊盘，使得中心焊盘IC芯片上的中心焊盘可以与引线框架的间隙对准以使得将中心焊盘IC芯片与引线框架的引线部分电连接的接合线通过。特征在于的封装允许施加到中心焊盘IC芯片的接合线的长度短，从而保持IC性能并节省制造成本，使得该多芯片IC封装结构比现有技术更有利。

6. 发明授权

US06667546B2 Ball grid array semiconductor package and substrate without power ring or ground ring 有权
标题翻译：球栅阵列半导体封装和衬底，无电源环或接地环
公开(公告)号：US06667546B2
公开(公告)日：2003-12-23
申请号：US10039884
申请日：2002-01-03
申请人： Chien-Ping Huang , Eric Ko , Chih-Ming Huang
发明人： Chien-Ping Huang , Eric Ko , Chih-Ming Huang
IPC分类号： H01L2310
CPC分类号： H01L24/85 , H01L23/3128 , H01L23/552 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/91 , H01L2224/05554 , H01L2224/371 , H01L2224/40095 , H01L2224/40225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49175 , H01L2224/73221 , H01L2224/8485 , H01L2224/85 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10161 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2224/78 , H01L2924/00 , H01L2924/00012
摘要： A ball grid array semiconductor package is proposed, wherein at least a chip is mounted on a substrate, and signal pads on the chip are electrically connected to signal fingers on the substrate by bonding wires. A power plate and a ground plate are each attached at two ends thereof respectively to predetermined positions on the chip and substrate, without interfering with the bonding wires. No power ring or ground ring is necessarily formed on the substrate, thereby reducing restriction on trace routability of the substrate. Further, with no provision of power wires or ground wires, short circuit of the bonding wires is less likely to occur, and thus production yield is enhanced. In addition, the power plate and ground plate provide shielding effect for protecting the chip against external electric-magnetic interference, and are partly in direct contact with the atmosphere for improving heat dissipating efficiency of the semiconductor package.
摘要翻译：提出了一种球栅阵列半导体封装，其中至少芯片安装在基板上，并且芯片上的信号焊盘通过接合线与基板上的信号指状电连接。功率板和接地板分别在其两端分别连接到芯片和基板上的预定位置，而不会妨碍接合线。在基板上不必形成功率环或接地环，从而减少对基板的微量可路由性的限制。此外，由于不设置电源线或接地线，因此不太可能发生接合线的短路，从而提高了生产率。此外，功率板和接地板提供屏蔽效果，用于保护芯片免受外部电磁干扰，并且部分地与大气直接接触，以提高半导体封装的散热效率。

7. 发明授权

US06414385B1 Quad flat non-lead package of semiconductor 有权
标题翻译：四边形非导线封装的半导体
公开(公告)号：US06414385B1
公开(公告)日：2002-07-02
申请号：US09475008
申请日：1999-12-30
申请人： Chien-Ping Huang , Eric Ko
发明人： Chien-Ping Huang , Eric Ko
IPC分类号： H01L2348
CPC分类号： H01L23/3114 , H01L23/4334 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01013 , H01L2924/01079 , H01L2924/10161 , H01L2924/14 , H01L2924/181 , H01L2924/18165 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： A Quad Flat Non-Lead package of semiconductor comprises a chip, a plurality of leads, and a molding compound. The chip has its active surface bonded to the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pad on the active surface of the chip. The leads are disposed at the periphery of the die pad. A plurality of bonding wires is used to electrically connect the top surface of the leads to the bonding pads. The molding compound encapsulates the chip, the die pad, the bonding wires, and a portion of the surface of the leads. In this way, the encapsulating process make the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the leads become the external connections of the package structure.
摘要翻译：半导体的四极扁平非引线封装包括芯片，多个引线和模制化合物。芯片具有与芯片焊盘接合的活性表面，并且芯片的面积小于芯片的面积，以露出芯片的有效表面上的焊盘。引线设置在管芯焊盘的周边。多个接合线用于将引线的顶表面电连接到接合焊盘。模塑料封装芯片，芯片焊盘，接合线以及引线表面的一部分。以这种方式，封装工艺使引线的侧表面，并且除了引线的底表面的引线接合突出区域之外的部分暴露以使引线变成封装结构的外部连接。

8. 发明授权

US06427976B1 Lead-frame-based chip-scale package and method of manufacturing the same 失效
标题翻译：基于引线框架的芯片级封装及其制造方法
公开(公告)号：US06427976B1
公开(公告)日：2002-08-06
申请号：US09464012
申请日：1999-12-15
申请人： Chien Ping Huang , Eric Ko
发明人： Chien Ping Huang , Eric Ko
IPC分类号： H01L2302
CPC分类号： H01L23/3114 , H01L23/4951 , H01L23/49551 , H01L24/48 , H01L2224/05599 , H01L2224/32014 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48463 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A lead-frame-based chip-scale package (CSP) structure and a method of manufacturing the same are proposed. The proposed CSP structure is characterized in the use of a specially-designed lead frame having an inner-lead part and an outer-lead part, which each inner lead being formed with a deformed portion. During the encapsulation process, an epoxy molding compound (EMC) is formed to encapsulate the semiconductor die and the inner-lead part. By the proposed CSP structure, both sides of the inner-lead part can be wrapped by the EMC due to it being raised by the deformed portion to within the EMC. As a result, during the lead-singulation process, the inner-lead part can be firmly supported in position, thereby reducing the occurrence of micro cracks in the EMC above the inner-lead part that would otherwise occur in the prior art.
摘要翻译：提出了一种基于引线框架的芯片级封装（CSP）结构及其制造方法。所提出的CSP结构的特征在于使用具有内引线部分和外引线部分的特别设计的引线框架，每个内引线形成有变形部分。在封装过程中，形成环氧树脂模塑料（EMC），以封装半导体芯片和内引线部分。通过提出的CSP结构，内引线部分的两侧可以被EMC包裹，由于其被变形部分升高到EMC内。结果，在引线切割过程中，内引线部分可以被牢固地支撑在适当的位置，从而减少在现有技术中将出现的内引线部分上方的EMC中的微裂纹的发生。

9. 发明授权

US06198171B1 Thermally enhanced quad flat non-lead package of semiconductor 有权
标题翻译：半导体热增强型四方扁平非引线封装
公开(公告)号：US06198171B1
公开(公告)日：2001-03-06
申请号：US09475003
申请日：1999-12-30
申请人： Chien-Ping Huang , Eric Ko
发明人： Chien-Ping Huang , Eric Ko
IPC分类号： H01L2348
CPC分类号： H01L23/4951 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/06135 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/18165 , H01L2924/00 , H01L2224/05599
摘要： A thermally enhanced quad flat non-lead package of semiconductor comprises a chip a plurality of leads, and a molding compound. The chip has its active surface bonded to the top surface of the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface of the chip. The leads are disposed at the periphery of the die pad wherein the bottom surface of the lead has a stepped structure with a relatively thin portion to form a wire-bonding protruded zone. A plurality of bonding wires is used to electrically connect the wire-bonding protruded zone of the leads to the bonding pads of the chip. The molding compound encapsulates the chip, bonding wires, the die pad, and a portion of the surface of the leads, but exposes the bottom surface of the die pad. In this way, the encapsulating process makes the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the lead become the external connecting points of the package structure.
摘要翻译：热增强型四边形半导体封装包括多个引线的芯片和模制化合物。该芯片具有与芯片焊盘的顶表面结合的活性表面，并且芯片焊盘的面积小于芯片的面积，以露出芯片的有源表面上的焊盘。引线设置在芯片焊盘的周边处，其中引线的底表面具有相对薄的部分的阶梯状结构，以形成引线接合突出区域。使用多个接合线将导线的引线接合突出区域电连接到芯片的接合焊盘。模塑料封装芯片，接合线，芯片焊盘和引线表面的一部分，但是露出芯片焊盘的底表面。以这种方式，封装工艺使引线的侧表面，并且除了引线的底表面的引线接合突出区域之外的部分暴露以使引线变成封装结构的外部连接点。

10. 发明授权

US4695164A Position detector and mount therefor for a centrifugal analyzer 失效
标题翻译：位置检测器，并安装在离心分析仪上
公开(公告)号：US4695164A
公开(公告)日：1987-09-22
申请号：US779520
申请日：1985-09-24
申请人： Maury Zivitz , Eric Ko , Mark Eslick
发明人： Maury Zivitz , Eric Ko , Mark Eslick
IPC分类号： B04B5/02 , G01D5/347 , G01N21/01 , G01N21/07 , G01N21/90 , G01N1/10
CPC分类号： G01D5/347 , G01N21/07
摘要： A relative position detector has a photodetector arrangement for providing light and responding to the intensity of the light when reflected thereto. A member such as a cylindrical pin having a surface reflective of the light, convex to the photodetector arrangement, and movable relative thereto reflectively sweeps the light across the photodetector arrangement for responding thereto to produce a continuously-curving response indicating with its peak the position detected. The continuously-curving response can be differentiated in a peak detector for even more precise position detection. A mount which may be used for the photodetector arrangement has a support member and a member having a lower coefficient of thermal expansion slidably supported thereon, except for one fixed point.
摘要翻译：相对位置检测器具有用于提供光并响应于其反射时的光的强度的光电检测器装置。具有反射光的表面的诸如圆柱形销的构件，对于光电检测器装置凸起并且可相对于其反射地反射地扫过光束以穿过光电检测器布置以对其进行响应以产生连续弯曲的响应，其指示其峰值检测到位置。可以在峰值检测器中区分连续弯曲的响应以进行更精确的位置检测。可以用于光电检测器装置的安装件具有支撑构件和除了一个固定点之外可滑动地支撑在其上的具有较低热膨胀系数的构件。

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