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1. 发明授权

US09117507B2 Multistage voltage regulator circuit 有权
标题翻译：多级稳压电路
公开(公告)号：US09117507B2
公开(公告)日：2015-08-25
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10 , G11C5/14 , G05F1/577 , G05F1/00
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： Circuit embodiments of a multistage voltage regulator circuit are presented, where a circuit includes a first stage that includes a first bias transistor having a current terminal coupled to a first regulated node. The circuit also includes a second stage that includes a second bias transistor having a current terminal coupled to a second regulated node. The circuit also includes a third stage including a third bias transistor having a current terminal coupled to a third node. The circuit also includes a control loop for regulating voltages at the first and second regulated nodes, where the second regulated node is connected to a control terminal of the first bias transistor; and where the first regulated node is connected to a control terminal of the third bias transistor.
摘要翻译：呈现多级电压调节器电路的电路实施例，其中电路包括第一级，其包括具有耦合到第一调节节点的电流端的第一偏置晶体管。电路还包括第二级，其包括具有耦合到第二调节节点的电流端子的第二偏置晶体管。电路还包括第三级，包括具有耦合到第三节点的电流端子的第三偏置晶体管。电路还包括用于调节第一和第二调节节点处的电压的控制回路，其中第二调节节点连接到第一偏置晶体管的控制端子; 并且其中第一调节节点连接到第三偏置晶体管的控制端子。

2. 发明授权

US08319548B2 Integrated circuit having low power mode voltage regulator 有权
标题翻译：集成电路具有低功耗模式电压调节器
公开(公告)号：US08319548B2
公开(公告)日：2012-11-27
申请号：US12622277
申请日：2009-11-19
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg , Hector Sanchez , Bradley J. Garni
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A voltage regulator regulates voltage at a node and has circuitry coupled to the node for providing a current to the node. A regulating transistor coupled between the node and a first power supply voltage terminal has a disabling transistor coupled in parallel and is selectively disabled by directly connecting the first power supply voltage terminal to the node. An inverting stage has an output connected to the regulating transistor. A load transistor has a first current electrode coupled to a second power supply voltage terminal, and a control electrode and second current electrode connected together and coupled to an input of the inverting stage. A sensing transistor has a first current electrode coupled to the second current electrode of the load transistor, a control electrode connected directly to the node and a second current electrode coupled to the first power supply voltage terminal.
摘要翻译：电压调节器调节节点处的电压，并且具有耦合到节点的电路以向节点提供电流。耦合在节点和第一电源电压端子之间的调节晶体管具有并联耦合的禁用晶体管，并且通过将第一电源电压端子直接连接到节点来选择性地禁止。反相级具有连接到调节晶体管的输出端。负载晶体管具有耦合到第二电源电压端子的第一电流电极和连接在一起并耦合到反相级的输入端的控制电极和第二电流电极。感测晶体管具有耦合到负载晶体管的第二电流电极的第一电流电极，直接连接到节点的控制电极和耦合到第一电源电压端子的第二电流电极。

3. 发明申请

US20120032655A1 MULTISTAGE VOLTAGE REGULATOR CIRCUIT 有权
标题翻译：多电平电压调节器电路
公开(公告)号：US20120032655A1
公开(公告)日：2012-02-09
申请号：US12853106
申请日：2010-08-09
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G05F1/00 , G05F1/577
摘要： A circuit including a multistage voltage regulator having a plurality of stages each including a regulated node and a bias transistor. The bias transistors and regulated nodes are configured to control the voltage of the regulated nodes. For at least some of the stages, the regulated nodes are coupled to voltage supply terminals of circuit modules of the stages.
摘要翻译：一种电路，包括具有多个级的多级稳压器，每个级包括调节节点和偏置晶体管。偏置晶体管和调节节点配置为控制受调节节点的电压。对于至少一些级，调节节点耦合到级的电路模块的电压端。

4. 发明授权

US08537625B2 Memory voltage regulator with leakage current voltage control 有权
标题翻译：内存电压调节器，具有漏电流电压控制
公开(公告)号：US08537625B2
公开(公告)日：2013-09-17
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C11/412
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

5. 发明申请

US20100207687A1 CIRCUIT FOR A LOW POWER MODE 有权
标题翻译：低功耗模式电路
公开(公告)号：US20100207687A1
公开(公告)日：2010-08-19
申请号：US12372997
申请日：2009-02-18
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译：电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。第三晶体管具有耦合到第一负载的输出的控制电极。第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。

6. 发明申请

US20120230126A1 MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL 有权
标题翻译：具有漏电流电压控制的存储电压调节器
公开(公告)号：US20120230126A1
公开(公告)日：2012-09-13
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C5/14 , G11C7/14 , G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

7. 发明授权

US07825720B2 Circuit for a low power mode 有权
标题翻译：低功耗模式电路
公开(公告)号：US07825720B2
公开(公告)日：2010-11-02
申请号：US12372997
申请日：2009-02-18
申请人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
发明人： Ravindraraj Ramaraju , David R. Bearden , Kenneth R. Burch , Charles E. Seaberg
IPC分类号： G05F1/10
CPC分类号： G05F1/56 , G11C5/147
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译：电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。第三晶体管具有耦合到第一负载的输出的控制电极。第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。

8. 发明申请

US20090237135A1 SCHMITT TRIGGER HAVING VARIABLE HYSTERESIS AND METHOD THEREFOR 审中-公开
标题翻译：具有可变HYSTERESIS及其方法的SCHMITT触发器
公开(公告)号：US20090237135A1
公开(公告)日：2009-09-24
申请号：US12053005
申请日：2008-03-21
申请人： Ravindraraj Ramaraju , Kenneth R. Burch
发明人： Ravindraraj Ramaraju , Kenneth R. Burch
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H03K2217/0018
摘要： A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.
摘要翻译：施密特触发器具有第一反相器，第二反相器，偏置装置和晶体管。变频器有一个输入和一个输出。第二反相器具有耦合到第一反相器的输出并具有输出的输入。偏置装置在第一输出端上提供第一偏置电压。偏置电压的大小由第一输入信号选择。晶体管具有耦合到第一电源端子的第一电流电极，耦合到第二反相器的输出的控制电极，耦合到第一反相器的输出的第二电流电极和耦合到第一输出端子的主体。偏置电压大小的可选性提供了施密特触发器的滞后的可选性。

9. 发明申请

US20080054943A1 Variable switching point circuit 审中-公开
标题翻译：可变开关点电路
公开(公告)号：US20080054943A1
公开(公告)日：2008-03-06
申请号：US11470342
申请日：2006-09-06
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Prashant U. Kenkare , William C. Moyer
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Prashant U. Kenkare , William C. Moyer
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/20
摘要： A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage (33, 34) coupled in parallel to a second inverter stage (35, 36) having extra PMOS (37) and NMOS (38) transistors connected to VDD and VSS, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal (40) generated by a delay element (39) coupled to the output of the first inverter stage. By using a delayed feed back signal (40) to control the extra PMOS and NMOS gates (37, 38), the switching point voltage of the first inverter stage (33, 34) is altered, depending on whether the input transitions are high-to-low or low-to-high.
摘要翻译：公开了一种可变开关点逆变器（30），其通过基于延迟输出来改变逆变器的P / N比来降低上升沿和下降沿输入电压（V IN IN）降低的阈值电压状态（V OUT OUT）。可变开关点反相器可以被构造为具有与具有额外的PMOS（37）和NMOS（38）晶体管的第二反相器级（35,36）并联耦合的第一反相器级（33,34）的CMOS集成电路，所述第二反相器级连接到其中分压PMOS和NMOS晶体管由延迟输出信号（40）控制，延迟输出信号（40）由耦合到该延迟元件（39）的延迟元件（39）产生，输出第一个反相器级。通过使用延迟反馈信号（40）来控制额外的PMOS和NMOS栅极（37,38），根据输入转换是否为高电平，第一反相器级（33,34）的开关点电压被改变，从低到高还是从低到高。

10. 发明授权

US09542334B2 Memory management unit TAG memory with CAM evaluate signal 有权
标题翻译：具有CAM评估信号的存储器管理单元TAG存储器
公开(公告)号：US09542334B2
公开(公告)日：2017-01-10
申请号：US13213831
申请日：2011-08-19
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： G06F12/10 , G06F9/38
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。来自操作数（111,113）的PGZ编码的地址位（0:51）被带有进位值（Cout48）到具有嵌入的部分A + B = K的紧凑位单元的内容寻址存储器阵列（114）在延迟评估信号的控制下产生两个投机命中/未命中信号的逻辑。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

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