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1. 发明申请

US20080054943A1 Variable switching point circuit 审中-公开
标题翻译：可变开关点电路
公开(公告)号：US20080054943A1
公开(公告)日：2008-03-06
申请号：US11470342
申请日：2006-09-06
申请人： Ravindraraj Ramaraju , Kenneth R. Burch , Prashant U. Kenkare , William C. Moyer
发明人： Ravindraraj Ramaraju , Kenneth R. Burch , Prashant U. Kenkare , William C. Moyer
IPC分类号： H03K19/094
CPC分类号： H03K19/017 , H03K19/20
摘要： A variable switching point inverter (30) is disclosed which lowers the threshold voltage lowered for both rising and falling edge input voltages (VIN) by changing the P/N ratio of the inverter based on the delayed output state (VOUT) of the inverter. The variable switching point inverter may be constructed as a CMOS integrated circuit with a first inverter stage (33, 34) coupled in parallel to a second inverter stage (35, 36) having extra PMOS (37) and NMOS (38) transistors connected to VDD and VSS, respectively, where the extra PMOS and NMOS transistors are controlled by the delayed output signal (40) generated by a delay element (39) coupled to the output of the first inverter stage. By using a delayed feed back signal (40) to control the extra PMOS and NMOS gates (37, 38), the switching point voltage of the first inverter stage (33, 34) is altered, depending on whether the input transitions are high-to-low or low-to-high.
摘要翻译：公开了一种可变开关点逆变器（30），其通过基于延迟输出来改变逆变器的P / N比来降低上升沿和下降沿输入电压（V IN IN）降低的阈值电压状态（V OUT OUT）。可变开关点反相器可以被构造为具有与具有额外的PMOS（37）和NMOS（38）晶体管的第二反相器级（35,36）并联耦合的第一反相器级（33,34）的CMOS集成电路，所述第二反相器级连接到其中分压PMOS和NMOS晶体管由延迟输出信号（40）控制，延迟输出信号（40）由耦合到该延迟元件（39）的延迟元件（39）产生，输出第一个反相器级。通过使用延迟反馈信号（40）来控制额外的PMOS和NMOS栅极（37,38），根据输入转换是否为高电平，第一反相器级（33,34）的开关点电压被改变，从低到高还是从低到高。

2. 发明授权

US07870400B2 System having a memory voltage controller which varies an operating voltage of a memory and method therefor 有权
标题翻译：具有改变存储器的工作电压的存储器电压控制器的系统及其方法
公开(公告)号：US07870400B2
公开(公告)日：2011-01-11
申请号：US11619070
申请日：2007-01-02
申请人： Prashant U. Kenkare , William C. Moyer
发明人： Prashant U. Kenkare , William C. Moyer
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is coupled to the system memory for varying the operating voltage of the system memory based upon whether the data processor or the peripheral is accessing the system memory. In another form a storage buffer is coupled to the memory for receiving and storing data from the memory. The buffer provides at least one signal that is used for either determining a rate at which the storage buffer is being emptied of data or a measure of fullness of the storage buffer. In one form the voltage controller varies the operating voltage of the memory based upon either the rate at which the storage buffer is being emptied of data or the measure of fullness.
摘要翻译：一种系统和方法可以节省处理系统的系统存储器的电量。外设，处理器，仲裁器和系统存储器耦合到系统通信总线，用于经由系统通信总线进行通信。在一种形式中，电压控制器耦合到系统存储器，用于基于数据处理器或外设是否访问系统存储器来改变系统存储器的工作电压。在另一形式中，存储缓冲器耦合到存储器，用于从存储器接收和存储数据。缓冲器提供至少一个用于确定存储缓冲器被清空的速率或存储缓冲器的满量程的信号。在一种形式中，电压控制器基于存储缓冲器被清空的速率或满量程来改变存储器的工作电压。

3. 发明申请

US20080162951A1 SYSTEM HAVING A MEMORY VOLTAGE CONTROLLER AND METHOD THEREFOR 有权
标题翻译：具有存储器电压控制器的系统及其方法
公开(公告)号：US20080162951A1
公开(公告)日：2008-07-03
申请号：US11619070
申请日：2007-01-02
申请人： Prashant U. Kenkare , William C. Moyer
发明人： Prashant U. Kenkare , William C. Moyer
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/13 , Y02D10/14
摘要： A system and method saves power in a system memory of a processing system. A peripheral, a processor, an arbiter and a system memory are coupled to a system communication bus for communicating via the system communication bus. In one form a voltage controller is coupled to the system memory for varying the operating voltage of the system memory based upon whether the data processor or the peripheral is accessing the system memory. In another form a storage buffer is coupled to the memory for receiving and storing data from the memory. The buffer provides at least one signal that is used for either determining a rate at which the storage buffer is being emptied of data or a measure of fullness of the storage buffer. In one form the voltage controller varies the operating voltage of the memory based upon either the rate at which the storage buffer is being emptied of data or the measure of fullness.
摘要翻译：一种系统和方法可以节省处理系统的系统存储器的电量。外设，处理器，仲裁器和系统存储器耦合到系统通信总线，用于经由系统通信总线进行通信。在一种形式中，电压控制器耦合到系统存储器，用于基于数据处理器或外设是否访问系统存储器来改变系统存储器的工作电压。在另一形式中，存储缓冲器耦合到存储器，用于从存储器接收和存储数据。缓冲器提供至少一个用于确定存储缓冲器被清空的速率或存储缓冲器的满量程的信号。在一种形式中，电压控制器基于存储缓冲器被清空的速率或满量程来改变存储器的工作电压。

4. 发明授权

US09081693B2 Data type dependent memory scrubbing 有权
标题翻译：数据类型相关内存擦除
公开(公告)号：US09081693B2
公开(公告)日：2015-07-14
申请号：US13588243
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/00 , G06F12/08 , G06F11/10
CPC分类号： G06F12/0895 , G06F11/106 , G06F11/1064 , Y02D10/13
摘要： A method for controlling a memory scrubbing rate based on content of the status bit of a tag array of a cache memory. More specifically, the tag array of a cache memory is scrubbed at smaller interval than the scrubbing rate of the storage arrays of the cache. This increased scrubbing rate is in appreciation for the importance of maintaining integrity of tag data. Based on the content of the status bit of the tag array which indicates modified, the corresponding data entry in the cache storage array is scrubbed accordingly. If the modified bit is set, then the entry in the storage array is scrubbed after processing the tag entry. If the modified bit is not set, then the storage array is scrubbed at a predetermined scrubbing interval.
摘要翻译：一种用于基于高速缓冲存储器的标签阵列的状态位的内容来控制存储器擦除速率的方法。更具体地说，高速缓冲存储器的标签阵列以比缓存的存储阵列的擦除速率更小的间隔进行擦除。对于保持标签数据完整性的重要性，这种提高的清洗率是值得赞赏的。基于指示被修改的标签阵列的状态位的内容，相应地擦除缓存存储阵列中的相应数据条目。如果修改的位被设置，则在处理标签条目之后擦除存储阵列中的条目。如果未设置修改的位，则以预定的擦洗间隔擦除存储阵列。

5. 发明授权

US08587356B2 Recoverable and reconfigurable pipeline structure for state-retention power gating 有权
标题翻译：用于状态保持功率门控的可恢复和可重新配置的管道结构
公开(公告)号：US08587356B2
公开(公告)日：2013-11-19
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

6. 发明申请

US20120036398A1 MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING 审中-公开
标题翻译：多核心数据处理器使用监控
公开(公告)号：US20120036398A1
公开(公告)日：2012-02-09
申请号：US13272725
申请日：2011-10-13
申请人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
发明人： William C. Moyer , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G06F11/14 , G06F9/312
CPC分类号： G06F9/505 , G06F16/217 , G06F2209/504 , G06F2209/508 , Y02D10/22
摘要： A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.
摘要翻译：具有多个处理器核心的数据处理器。多个处理器核心中的每一个的累积使用信息被存储在数据处理器内的存储设备中，其中累积的使用信息指示多个处理器核心的每个处理器核心的累积使用。处理器使用累积的使用信息来选择处理器核心来执行处理器操作。

7. 发明申请

US20080056049A1 METHOD FOR POWERING AN ELECTRONIC DEVICE AND CIRCUIT 有权
标题翻译：用于为电子设备和电路供电的方法
公开(公告)号：US20080056049A1
公开(公告)日：2008-03-06
申请号：US11469084
申请日：2006-08-31
申请人： William C. Moyer , Ravindraraj Ramaraju
发明人： William C. Moyer , Ravindraraj Ramaraju
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50
摘要： A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.
摘要翻译：电路和方法在低电压工作模式下有效地为静态存储元件供电。静态存储元件以静态存储元件的活动模式中的第一电压电平供电。静态存储元件使用交替的第一和第二相以低功率模式供电。在低功率模式的第一阶段期间为静态存储元件供电包括为静态存储元件供电或处于第二电压电平以下，其中在低功率模式的第二阶段期间为静态存储元件供电包括给静态存储元件供电比第二电压电平高的电压电平。在另一种形式中，使用低功率操作的两种模式，其中第一模式使用比第二模式更少的功率有效的操作，但是两者都比正常功率模式更有效。

8. 发明申请

US20140052924A1 Selective Memory Scrubbing Based on Data Type 有权
标题翻译：基于数据类型的选择性内存清理
公开(公告)号：US20140052924A1
公开(公告)日：2014-02-20
申请号：US13588194
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/12
CPC分类号： G06F12/12 , G06F12/0893 , G06F2212/1036 , Y02D10/13
摘要： A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).
摘要翻译：一种通过有选择地为单个存储体级别的高速缓存存储器控制存储器擦除速率来最小化高速缓存内的软错误率的方法。更具体地，本公开涉及基于例如高速缓存行的状态信息内的修改指示的状态来维持预定顺序和将高速缓存的所有修改信息存储在高速缓存的方式的子集中的处理。高速缓冲存储器控制器包括一个存储器擦除控制器，该存储器擦除控制器被编程为与具有干净信息的其余方式（即，存储信息的信息相比较）以更小的间隔（即，更频繁地）用修改的信息擦除子集的子集在主存储器内部与缓存中存储的信息相干）。

9. 发明申请

US20130154707A1 RECOVERABLE AND RECONFIGURABLE PIPELINE STRUCTURE FOR STATE-RETENTION POWER GATING 有权
标题翻译：用于状态保持功率补偿的可恢复和可重新配置的管道结构
公开(公告)号：US20130154707A1
公开(公告)日：2013-06-20
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

10. 发明授权

US07400545B2 Storage circuit with efficient sleep mode and method 失效
标题翻译：具有高效睡眠模式和方法的存储电路
公开(公告)号：US07400545B2
公开(公告)日：2008-07-15
申请号：US11469074
申请日：2006-08-31
申请人： Ravindraraj Ramaraju , William C. Moyer
发明人： Ravindraraj Ramaraju , William C. Moyer
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/413
摘要： A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.
摘要翻译：电路和方法在低电压工作模式下有效地为静态存储元件供电。静态存储元件以静态存储元件的活动模式中的第一电压电平供电。静态存储元件使用交替的第一和第二相以低功率模式供电。在低功率模式的第一阶段期间为静态存储元件供电包括为静态存储元件供电或处于第二电压电平以下，其中在低功率模式的第二阶段期间为静态存储元件供电包括给静态存储元件供电比第二电压电平高的电压电平。在另一种形式中，使用低功率操作的两种模式，其中第一模式使用比第二模式更少的功率有效的操作，但是两者都比正常功率模式更有效。

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