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1. 发明申请

US20140269131A1 MEMORY WITH POWER SAVINGS FOR UNNECESSARY READS 有权
标题翻译：具有省电功能的记忆用于不必要的阅读
公开(公告)号：US20140269131A1
公开(公告)日：2014-09-18
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

2. 发明授权

US09317087B2 Memory column drowsy control 有权
标题翻译：内存列困倦控制
公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

3. 发明授权

US09225337B2 Temperature threshold circuit with hysteresis 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US09225337B2
公开(公告)日：2015-12-29
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： G01K1/02 , H03K21/10 , G01K7/00 , H03K21/38 , G01K13/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

4. 发明授权

US09117498B2 Memory with power savings for unnecessary reads 有权
标题翻译：记忆功能，节省了不必要的读数
公开(公告)号：US09117498B2
公开(公告)日：2015-08-25
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08 , G11C8/12
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

5. 发明授权

US06928005B2 Domino comparator capable for use in a memory array 有权
公开(公告)号：US06928005B2
公开(公告)日：2005-08-09
申请号：US10703657
申请日：2003-11-05
申请人： Ravindraraj Ramaraju , George P. Hoekstra
发明人： Ravindraraj Ramaraju , George P. Hoekstra
IPC分类号： G11C7/00 , G11C11/00 , G11C15/00
CPC分类号： G11C15/00
摘要： A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.

6. 发明授权

US09672938B2 Memory with redundancy 有权
公开(公告)号：US09672938B2
公开(公告)日：2017-06-06
申请号：US14258730
申请日：2014-04-22
申请人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
发明人： George P. Hoekstra , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C7/00 , G11C29/44 , G11C29/00 , G11C29/12
CPC分类号： G11C29/44 , G11C29/12 , G11C29/83
摘要： Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.

7. 发明申请

US20160062656A1 Command Set Extension for Non-Volatile Memory 审中-公开
标题翻译：非易失性存储器的命令集扩展
公开(公告)号：US20160062656A1
公开(公告)日：2016-03-03
申请号：US14471871
申请日：2014-08-28
申请人： Ravindraraj Ramaraju , George P. Hoekstra
发明人： Ravindraraj Ramaraju , George P. Hoekstra
IPC分类号： G06F3/06
CPC分类号： G11C16/10 , G11C16/14 , G11C16/3445
摘要： A method and apparatus are provided for generating an adjusted internal electrical parameter for accessing a NAND Flash memory array based on an adjustment control parameter conveyed by a memory access instruction, where the memory access instruction is compliant with an Open NAND Flash Interface (ONFI) protocol to include a two command cycle sequence to specify a command for accessing the NAND Flash memory with the adjusted internal electrical parameter.
摘要翻译：提供了一种方法和装置，用于根据由存储器访问指令传送的调整控制参数产生用于访问NAND闪存阵列的经调整的内部电参数，其中存储器访问指令符合开放NAND闪存接口（ONFI）协议包括两个命令循环序列，以指定用调整的内部电气参数访问NAND闪存的命令。

8. 发明授权

US09224439B2 Memory with word line access control 有权
标题翻译：内存带字线访问控制
公开(公告)号：US09224439B2
公开(公告)日：2015-12-29
申请号：US13537209
申请日：2012-06-29
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/00 , G11C7/10 , G11C8/10 , G11C11/418
CPC分类号： G11C7/1075 , G11C8/10 , G11C11/418
摘要： A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.
摘要翻译：具有存储器阵列的存储器具有多个字线，耦合到字线的多个位单元以及耦合到该字线的多个控制存储单元。多个字线的每个字线具有耦合到其上的控制存储单元，并且每个控制存储单元具有输出。存储器还具有耦合到多个字线的多个逻辑电路。每个控制存储器单元的输出耦合到多个逻辑电路中的对应的一个。如果耦合到所选字线的控制存储单元的输出处于第一逻辑状态，则多个逻辑电路防止访问由行地址选择的字线。

9. 发明申请

US20150244375A1 TEMPERATURE THRESHOLD CIRCUIT WITH HYSTERESIS 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US20150244375A1
公开(公告)日：2015-08-27
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： H03K21/10 , G01K7/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

10. 发明授权

US08487657B1 Dynamic logic circuit 有权
标题翻译：动态逻辑电路
公开(公告)号：US08487657B1
公开(公告)日：2013-07-16
申请号：US13484870
申请日：2012-05-31
申请人： George P. Hoekstra , Ravindraraj Ramaraju , Maciej Bajkowski
发明人： George P. Hoekstra , Ravindraraj Ramaraju , Maciej Bajkowski
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.
摘要翻译：动态逻辑电路包括在动态节点和用于接收多个逻辑信号的第一电源端子之间的N沟道晶体管堆叠。 P沟道时钟晶体管耦合在第二电源端子和动态节点之间用于接收时钟信号。 N沟道时钟晶体管与N沟道堆叠串联，并且位于动态节点和第一电源端子之间用于接收时钟信号。保持器晶体管具有耦合到动态节点的第一电流电极，耦合到第二电源端子的第二电流电极和控制电极。静态逻辑电路具有用于响应逻辑信号的状态提供输出的输出。输出耦合到保持晶体管的控制电极。

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