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1. 发明申请

US20060047935A1 Data processing system having translation lookaside buffer valid bits with lock and method therefor 有权
标题翻译：具有翻译后备缓冲器有效位的数据处理系统及其锁定方法
公开(公告)号：US20060047935A1
公开(公告)日：2006-03-02
申请号：US10928399
申请日：2004-08-27
申请人： Ravindraraj Ramaraju , David Burgess , Troy Cooper , Eric Fiene , George Hoekstra
发明人： Ravindraraj Ramaraju , David Burgess , Troy Cooper , Eric Fiene , George Hoekstra
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/1027
摘要： A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).
摘要翻译：系统（10）翻译存储器地址。处理电路（12）向具有多个存储的有效地址的存储阵列（14,16）提供有效地址，所述多个存储的有效地址中的每一个具有相应的一对锁定位和有效位。将输出标签值和单个有效位提供给比较器（18）。锁定位定义系统执行的两个预定任务类别之一。单个有效位适用于两个预定类别的任务。锁定位限定单个有效位的清除。比较器分别将输出标签值和单个有效位与预定的有效地址和预定位值进行比较。当发生匹配以验证由物理地址阵列（20）提供的物理地址时，提供输出命中信号。

2. 发明申请

US20050286327A1 Memory device with a data hold latch 有权
标题翻译：具有数据保持锁存器的存储器件
公开(公告)号：US20050286327A1
公开(公告)日：2005-12-29
申请号：US10865274
申请日：2004-06-10
申请人： Ravindraraj Ramaraju , George Hoekstra , Prashant Kenkare
发明人： Ravindraraj Ramaraju , George Hoekstra , Prashant Kenkare
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C7/12 , G11C8/16
摘要： A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line and a first output and a second output to provide complementary latched values dependent upon a value of the data line. For each latch of the plurality of latches, the first output is coupled to a first bit line of a pair of the plurality such that a value of the first bit line is continuously determined by the first output during memory device operation and the second output is coupled to a second bit line of the pair such that a value of the second bit line is continuously determined by the second output during memory device operation.
摘要翻译：存储器件包括多对互补位线和多个锁存电路。多对互补位线对中的每一对耦合到一列存储单元。每个锁存电路具有耦合到数据线和第一输出和第二输出的输入，以提供取决于数据线的值的互补锁存值。对于多个锁存器中的每个锁存器，第一输出耦合到一对多对的第一位线，使得在存储器件操作期间第一位线的值被第一输出连续地确定，并且第二输出是耦合到该对的第二位线，使得在存储器件操作期间第二位线的值由第二输出连续地确定。

3. 发明申请

US20050105324A1 Domino comparator capable for use in a memory array 有权
标题翻译： Domino比较器可用于存储器阵列
公开(公告)号：US20050105324A1
公开(公告)日：2005-05-19
申请号：US10703657
申请日：2003-11-05
申请人： Ravindraraj Ramaraju , George Hoekstra
发明人： Ravindraraj Ramaraju , George Hoekstra
IPC分类号： G11C7/00 , G11C11/00 , G11C15/00
CPC分类号： G11C15/00
摘要： A memory including a NOR logic gate having an input coupled to a bitline (BL) and an input to receive the complement of the data value (DATABAR). The memory also including a NOR logic gate having an input coupled to the bitline bar (BLBAR) and an input to receive the data value (DATA). A combine stage is also included having an input coupled to an output of the NOR logic gate, an input coupled to an output of the NOR logic gate, and an output to provide a miss indicator (MISS). The miss indicator (MISS) indicates when a value on the bitline (BL) does not match the data value (DATA). The memory also comprising a plurality of bitcells coupled to the bitline (BL) and bitline bar (BLBAR), where each of the plurality of bitcells is coupled to a corresponding word line.
摘要翻译：包括具有耦合到位线（BL）的输入的NOR逻辑门和用于接收数据值（DATABAR）的补码的输入的存储器。存储器还包括具有耦合到位线条（BLBAR）的输入的NOR逻辑门和用于接收数据值（DATA）的输入。组合级还包括具有耦合到NOR逻辑门的输出的输入，耦合到NOR逻辑门的输出的输入和用于提供未命中指示符（MISS）的输出。错误指示符（MISS）指示位线（BL）上的值与数据值（DATA）不匹配的时间。存储器还包括耦合到位线（BL）和位线条（BLBAR）的多个位单元，其中多个位单元中的每一个耦合到对应的字线。

4. 发明申请

US20070222480A1 Circuit and method for latch bypass 有权
标题翻译：闩锁旁路的电路和方法
公开(公告)号：US20070222480A1
公开(公告)日：2007-09-27
申请号：US11388921
申请日：2006-03-24
申请人： Maciej Bajkowski , George Hoekstra , Prashant Kenkare , Ravindraraj Ramaraju
发明人： Maciej Bajkowski , George Hoekstra , Prashant Kenkare , Ravindraraj Ramaraju
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , G11C29/56 , G11C2029/5602
摘要： A device includes a first combinatorial logic stage having a first input to receive a first data value, a second input to receive a bypass value and an output to provide one of a representation of the first data value or a first predetermined value based on the bypass value. The device further includes a latch stage having a first input to receive a second data value, a second input to receive the bypass value and an output to provide one of a latched representation of the second data value or a second predetermined value based on the bypass value. The device additionally includes a second combinatorial logic stage having a first input coupled to the output of the first combinatorial logic stage, a second input coupled to the output of the latch stage, and an output.
摘要翻译：一种设备包括具有第一输入以接收第一数据值的第一组合逻辑级，用于接收旁路值的第二输入和用于提供第一数据值的表示或基于旁路的第一预定值之一的输出值。该装置还包括具有第一输入以接收第二数据值的锁存级，用于接收旁路值的第二输入和用于提供基于旁路的第二数据值的锁存表示或第二预定值之一的输出值。该装置还包括第二组合逻辑级，其具有耦合到第一组合逻辑级的输出的第一输入，耦合到锁存级的输出的第二输入和输出。

5. 发明申请

US20070094479A1 System and method for memory array access with fast address decoder 有权
标题翻译：具有快速地址解码器的存储器阵列访问的系统和方法
公开(公告)号：US20070094479A1
公开(公告)日：2007-04-26
申请号：US11257932
申请日：2005-10-25
申请人： David Bearden , George Hoekstra , Ravindraraj Ramaraju
发明人： David Bearden , George Hoekstra , Ravindraraj Ramaraju
IPC分类号： G06F9/34
CPC分类号： G06F9/355 , G06F9/345
摘要： A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using wordline generators resulting in a plurality of possible memory array entry addresses. In parallel with the PGZO operations, a carry value is generated using other bits in the operands. The result of the carry operation determines which of the possible memory array entries is selected from the memory array.
摘要翻译：使用基地址和偏移地址提供访问存储器阵列中的条目的方法和数据处理系统，而不添加基址和偏移地址。对操作数的地址位执行PGZO编码。使用字线生成器来评估PGZO值，得到多个可能的存储器阵列入口地址。与PGZO操作并行，使用操作数中的其他位生成进位值。进位操作的结果确定从存储器阵列中选择哪个可能的存储器阵列条目。

6. 发明申请

US20060022714A1 Dynamic latch having integral logic function and method therefor 有权
标题翻译：具有积分逻辑功能的动态锁存器及其方法
公开(公告)号：US20060022714A1
公开(公告)日：2006-02-02
申请号：US10902204
申请日：2004-07-29
申请人： Ravindraraj Ramaraju , George Hoekstra , Jeremiah Palmer
发明人： Ravindraraj Ramaraju , George Hoekstra , Jeremiah Palmer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A circuit (50) that receives dynamic signals performs both logic and latching to achieve high speed operation. The circuit has a clock that defines both an evaluation phase and a precharge phase in which the dynamic signals are evaluated during the evaluation phase. The circuit (50) functions by precharging a latch node (INT) during the evaluation phase then performing evaluation as well during the evaluation phase. The evaluation results in providing a valid logic state to the latch node. A latch circuit (54) latches this valid state during the precharge phase and holds it in this valid state during the precharge phase. This can be adapted to select which one of the dynamic signals is to be coupled and latched on the latch node (INT).
摘要翻译：接收动态信号的电路（50）执行逻辑和锁存以实现高速操作。电路具有定义评估阶段和预充电阶段的时钟，其中动态信号在评估阶段被评估。电路（50）通过在评估阶段期间对锁存节点（INT）进行预充电来起作用，然后在评估阶段期间执行评估。评估导致向锁存节点提供有效的逻辑状态。锁存电路（54）在预充电阶段期间锁存该有效状态，并且在预充电阶段将其保持在该有效状态。这可以适于选择哪个动态信号被耦合并锁存在锁存节点（INT）上。

7. 发明授权

US5053990A Program/erase selection for flash memory 失效
标题翻译： FLASH存储器的程序/擦除选择
公开(公告)号：US5053990A
公开(公告)日：1991-10-01
申请号：US157361
申请日：1988-02-17
申请人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
发明人： Jerry A. Kreifels , Alan Baker , George Hoekstra , Virgil N. Kynett , Steven Wells , Mark Winston
IPC分类号： G11C17/00 , G06F12/00 , G11C16/02 , G11C16/10 , G11C16/16 , G11C16/34 , G11C29/00 , G11C29/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/3459
摘要： A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.
摘要翻译：一种半导体闪存EPROM / EEPROM器件，包括用于在数据线上接收指令并向存储器提供控制信号以提供编程和擦除功能的命令端口，编程和擦除存储器的方法。程序序列包括在第一写周期期间设置程序命令，执行第二写周期以将地址寄存器加载到地址寄存器和数据到数据寄存器，在程序周期期间进行编程以及在第三写入期间写入程序验证命令写周期以在读周期中验证编程数据。擦除序列包括在第一写周期期间写入建立擦除命令，在擦除周期期间提供擦除的第二写周期期间的擦除命令，在第三写周期期间写入擦除验证命令，该第三写周期还解决存储器并在读周期期间提供擦除验证。擦除和编程周期都提供测量的增量擦除和编程。

8. 发明授权

US5751741A Rate-adapted communication system and method for efficient buffer utilization thereof 失效
标题翻译：速率适应通信系统及其高效缓冲利用方法
公开(公告)号：US5751741A
公开(公告)日：1998-05-12
申请号：US754768
申请日：1996-11-20
申请人： Raymond Paul Voith , Sujit Sudhaman , George Hoekstra
发明人： Raymond Paul Voith , Sujit Sudhaman , George Hoekstra
IPC分类号： H04B7/26 , H04L25/05 , H03M13/22
CPC分类号： H04B7/2659 , H04L25/05 , Y10S370/914
摘要： A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).
摘要翻译：收发器（34）包括速率自适应缓冲器（74），其将以4.0kHz速率接收的数据流与以4.05kHz速率发送的数据流同步。收发器（34）的发送部分（62）使用单个速率适配缓冲器执行速率自适应。发送部分（62）包括四个自主模块，它们能够彼此独立地访问速率自适应缓冲器（74）中的数据。这四个模块包括CRC加扰器（72），FEC编码器（76），交织器（78）和星座编码器（80）。定时控制器（84）防止对速率适配缓冲器（74）的访问的争用。此外，四个模块中的每个模块足够快地执行其各自的功能，以防止速率适配缓冲器（74）中的溢出或下溢条件。接收部分（64）的功能类似于发送部分（62）。

9. 发明申请

US20050110522A1 Multistage dynamic domino circuit with internally generated delay reset clock 审中-公开
标题翻译：具有内部产生的延迟复位时钟的多级动态多米诺骨架电路
公开(公告)号：US20050110522A1
公开(公告)日：2005-05-26
申请号：US10718891
申请日：2003-11-21
申请人： George Hoekstra
发明人： George Hoekstra
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A multistage dynamic domino circuit includes a footed dynamic domino stage, a footless dynamic domino stage, and a internal delay circuit. The footed dynamic domino stage includes a first precharge circuit, evaluation logic, and a data output coupled to the evaluation logic. The footless dynamic domino stage includes evaluation logic including a data input coupled to the data output of the footed dynamic domino stage and a second precharge circuit. The second precharge circuit includes a first precharge device including a first current terminal and a control terminal coupled to a clock line. The second precharge circuit further includes a second precharge device including a first current terminal coupled to the first current terminal of first precharge device and a control terminal. The delay circuit includes an input coupled to the clock line and an output coupled to the control terminal of the second precharge device to provide a delayed version of a clock signal provided at the input of the delay circuit.
摘要翻译：多级动态多米诺骨牌包括脚踏动态多米诺骨牌阶段，无脚踏动态多米诺骨牌阶段和内部延迟电路。有脚动态多米诺骨牌阶段包括第一预充电电路，评估逻辑和耦合到评估逻辑的数据输出。无脚动态多米诺骨牌阶段包括评估逻辑，包括耦合到有脚动态多米诺舞台的数据输出的数据输入和第二预充电电路。第二预充电电路包括第一预充电装置，其包括第一电流端子和耦合到时钟线的控制端子。第二预充电电路还包括第二预充电装置，其包括耦合到第一预充电装置的第一电流端子的第一电流端子和控制端子。延迟电路包括耦合到时钟线的输入和耦合到第二预充电装置的控制端的输出，以提供在延迟电路的输入处提供的时钟信号的延迟版本。

10. 发明授权

US4841482A Leakage verification for flash EPROM 失效
标题翻译：闪存EPROM的泄漏验证
公开(公告)号：US4841482A
公开(公告)日：1989-06-20
申请号：US157364
申请日：1988-02-17
申请人： Jerry A. Kreifels , George Hoekstra
发明人： Jerry A. Kreifels , George Hoekstra
IPC分类号： G11C16/34 , G11C29/02 , G11C29/50
CPC分类号： G11C16/345 , G11C16/344 , G11C29/02 , G11C29/025 , G11C29/50 , G11C16/04 , G11C2029/5006
摘要： A circuit and method for verifying leakage in a flash EPROM/EEPROM memory cell which is fabricated on a silicon substrate having floating gate. A word line coupled to the control gate of the memory cell is typically at ground potential, but during a test mode a positive voltage is placed on the control gate and leakage current at the drain is measured. A good cell will typically have zero or negligible drain leakage current, however, a cell which is susceptible to being overerased will exhibit appreciable leakage current. A circuit is implemented on the chip with the memory for switching a positive voltage onto the word line during the test mode.
摘要翻译：一种用于验证在具有浮动栅极的硅衬底上制造的闪存EPROM / EEPROM存储单元中的泄漏的电路和方法。耦合到存储单元的控制栅极的字线通常处于地电位，但是在测试模式期间，在控制栅极上放置正电压，并测量漏极处的漏电流。良好的电池通常具有零或可忽略的漏极漏电流，然而，容易被过度烧蚀的电池将会呈现明显的漏电流。在芯片上实现一个电路，用于在测试模式期间将正电压切换到字线上的存储器。

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