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1. 发明授权

US06711652B2 Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data 失效
标题翻译：非均匀内存访问（NUMA）数据处理系统，提供修改数据的远程释放的精确通知
公开(公告)号：US06711652B2
公开(公告)日：2004-03-23
申请号：US09885999
申请日：2001-06-21
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0813
摘要： A non-uniform memory access (NUMA) computer system includes a remote node coupled by a node interconnect to a home node including a home system memory. The remote node includes a plurality of snoopers coupled to a local interconnect. The plurality of snoopers includes a cache that caches a cache line corresponding to but modified with respect to data resident in the home system memory. The cache has a cache controller that issues a deallocate operation on the local interconnect in response to deallocating the modified cache line. The remote node further includes a node controller, coupled between the local interconnect and the node interconnect, that transmits the deallocate operation to the home node with an indication of whether or not a copy of the cache line remains in the remote node following the deallocation. In this manner, the local memory directory associated with the home system memory can be updated to precisely reflect which nodes hold a copy of the cache line.
摘要翻译：非均匀存储器访问（NUMA）计算机系统包括通过节点互连耦合到包括归属系统存储器的家庭节点的远程节点。远程节点包括耦合到本地互连的多个窥探者。多个窥探器包括高速缓存，其缓存对于相对于驻留在本地系统存储器中的数据而被修改的高速缓存线。高速缓存具有缓存控制器，其响应于释放修改的高速缓存线而在本地互连上发出释放操作。远程节点还包括耦合在本地互连和节点互连之间的节点控制器，其将取消分配操作发送到家庭节点，并指示在解除分配之后高速缓存行的副本是否保留在远程节点中。以这种方式，可以更新与家庭系统存储器相关联的本地存储器目录，以精确地反映哪些节点保存高速缓存行的副本。

2. 发明授权

US06662275B2 Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache 有权
公开(公告)号：US06662275B2
公开(公告)日：2003-12-09
申请号：US09782578
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0848
摘要： A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

3. 发明授权

US06662216B1 Fixed bus tags for SMP buses 失效
标题翻译：用于SMP总线的固定总线标签
公开(公告)号：US06662216B1
公开(公告)日：2003-12-09
申请号：US08839478
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to a first aspect of the present invention, a data processing system is provided that includes a communication network to which multiple devices are coupled. A first of the multiple devices includes a number of requestors (or queues), which are each permanently assigned a respective one of a number of unique tags. In response to a communication request by a requestor within the first device, a tag assigned to the requestor is transmitted on the communication network in conjunction with the requested communication transaction. According to a second aspect of the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明的第一方面，提供一种数据处理系统，其包括多个设备耦合到的通信网络。多个设备中的第一个包括多个请求者（或队列），每个请求者（或队列）被永久地分配多个唯一标签中的相应的一个。响应于第一设备内的请求者的通信请求，分配给请求者的标签与所请求的通信事务一起在通信网络上发送。根据本发明的第二方面，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

4. 发明授权

US06629214B1 Extended cache coherency protocol with a persistent “lock acquired” state 失效
标题翻译：具有持续“锁获取”状态的扩展缓存一致性协议
公开(公告)号：US06629214B1
公开(公告)日：2003-09-30
申请号：US09437186
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3857
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的缓存状态允许优化缓存状态转换序列。特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器一个修改。通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

5. 发明授权

US06553462B2 Multiprocessor computer system with sectored cache line mechanism for load and store operations 失效
公开(公告)号：US06553462B2
公开(公告)日：2003-04-22
申请号：US09753057
申请日：2000-12-28
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.

6. 发明授权

US06507880B1 Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens 失效
标题翻译：总线协议，总线主机和总线监听器，用于执行使用多个令牌的全局操作
公开(公告)号：US06507880B1
公开(公告)日：2003-01-14
申请号：US09435927
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1300
CPC分类号： G06F12/0831
摘要： In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits one of a plurality of tokens required to complete the global operation and identifies the global operation to be processed with the token, if granted. Bus snoopers contain a number of snooper queues for global operations equal to the number of global operation tokens employed within the multiprocessor system. A bus snooper, upon detecting a combined token and operation request, begins speculatively processing the operation if the snooper is not already busy. Before completing the operation, the snooper watches for a combined response with a token number acknowledging either the combined request or a subsequent token request from the same processor, which indicates that the originating bus master has been granted a token for completing a global operation. Otherwise, a combined response acknowledging an operation request containing the token number implies release of the granted token.
摘要翻译：响应于启动全局操作的需要，多处理器系统内的总线主机在耦合到总线主机的总线上发出组合的令牌和操作请求。组合的令牌和操作请求请求完成全局操作所需的多个令牌中的一个令牌，并且如果被授权则标识要用令牌处理的全局操作。总线侦听器包含多个用于全局操作的侦听队列，等于在多处理器系统中使用的全局操作令牌的数量。一旦检测到组合的令牌和操作请求，总线侦听器开始推测性地处理该操作，如果该侦听器尚未忙。在完成操作之前，窥探者使用令牌号来识别来自同一处理器的组合请求或后续令牌请求的组合响应，其指示始发总线主机已经被授予用于完成全局操作的令牌。否则，确认包含令牌号的操作请求的组合响应意味着释放所授予的令牌。

7. 发明授权

US06502171B1 Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data 失效
标题翻译：具有组合侦听响应的多处理器系统总线显式通知窥探者围绕数据
公开(公告)号：US06502171B1
公开(公告)日：2002-12-31
申请号：US09368231
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： In cancelling the cast out portion of a combined operation including a data access related to the cast out, the combined response logic explicitly directs a horizontal storage device at the same level as the storage device initiating the combined operation to allocate and store either the cast out or target data. A horizontal storage device having available space—i.e., an invalid or modified data element in a congruence class for the victim—stores either the target or the cast out data for subsequent access by an intervention. Cancellation of the cast out thus defers any latency associated with writing the cast out victim to system memory while maximizing utilization of available storage with acceptable tradeoffs in data access latency.
摘要翻译：组合响应逻辑在取消组合操作包括与丢弃相关的数据访问的组合操作时，明确指示与启动组合操作的存储设备处于同一级别的水平存储设备，以分配和存储任务或目标数据。具有可用空间的水平存储设备（即，用于受害者的同余类中的无效或修改的数据元素）存储目标或丢弃数据以供随后的干预访问。取消投票，从而延迟与将丢弃的受害者写入系统内存相关的任何延迟，同时最大限度地利用可用存储在数据访问延迟中具有可接受的折中。

8. 发明授权

US06502168B1 Cache having virtual cache controller queues 失效
标题翻译：缓存具有虚拟缓存控制器队列
公开(公告)号：US06502168B1
公开(公告)日：2002-12-31
申请号：US09404028
申请日：1999-09-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F11/349 , G06F12/0831 , G06F2201/885
摘要： According to the present invention, a data processing system includes a cache having a cache directory. A status indication indicative of the status of at least one of a plurality of data entries in the cache is stored in the cache directory. In response to receipt of a cache operation request, a determination is made whether to update the status indication. In response to the determination that the status indication is to be updated, the status indication is copied into a shadow register and updated. The status indication is then written back into the cache directory at a later time. The shadow register thus serves as a virtual cache controller queue that dynamically mimics a cache directory entry without functional latency.
摘要翻译：根据本发明，数据处理系统包括具有高速缓存目录的高速缓存。指示高速缓存中的多个数据条目中的至少一个的状态的状态指示被存储在高速缓存目录中。响应于接收到高速缓存操作请求，确定是否更新状态指示。响应于要更新状态指示的确定，状态指示被复制到影子寄存器并被更新。状态指示随后被写回缓存目录。因此，影子寄存器用作虚拟高速缓存控制器队列，其动态地模拟高速缓存目录条目而没有功能延迟。

9. 发明授权

US06487637B1 Method and system for clearing dependent speculations from a request queue 失效
标题翻译：从请求队列中清除相关推测的方法和系统
公开(公告)号：US06487637B1
公开(公告)日：2002-11-26
申请号：US09364408
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1300
CPC分类号： G06F9/30047 , G06F9/3802 , G06F9/383 , G06F9/3842 , G06F12/0897
摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. Further branch predictions or stream associations that were made based on an earlier speculative choice are linked by using a tag pool which assigns a bit fields in the tag pool entries to the level of speculation depth. Each entry shares in common the bit field values associated with earlier branches or stream associations. When a branch or stream predicted entry is no longer needed, that entry can be cancelled and all entries that were to be loaded dependent on that entry can likewise be cancelled by walking through all entries sharing the bit fields corresponding to the speculation depth of the cancelled entry and tagging those entries as invalid.
摘要翻译：一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测他们可能需要。通过使用将标签池条目中的位字段分配给投机深度的标签池来链接根据较早的推测选择进行的进一步分支预测或流关联。每个条目共享与早期分支或流关联相关联的比特字段值。当不再需要分支或流预测条目时，可以取消该条目，并且可以通过遍历与所取消的投机深度相对应的比特字段的所有条目，来取消根据该条目加载的所有条目输入并标记这些条目为无效。

10. 发明授权

US06438656B1 Method and system for cancelling speculative cache prefetch requests 失效
标题翻译：用于取消推测性高速缓存预取请求的方法和系统
公开(公告)号：US06438656B1
公开(公告)日：2002-08-20
申请号：US09364574
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F9/3804 , G06F9/30047 , G06F9/383 , G06F9/3842 , G06F9/3857 , G06F9/3861 , G06F12/0862 , G06F12/0897
摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. After a predetermined number of cycles has elapsed, the speculative load request is cancelled if the request has not already been completed.
摘要翻译：一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。本发明适用于作为操作数数据或指令的值。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测他们可能需要。在经过预定数量的周期之后，如果请求尚未完成，则推测加载请求被取消。

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