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1. 发明授权

US06385702B1 High performance multiprocessor system with exclusive-deallocate cache state 失效
标题翻译：具有独占解除缓存状态的高性能多处理器系统
公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译：高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值的计算机系统。如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

2. 发明授权

US06629214B1 Extended cache coherency protocol with a persistent “lock acquired” state 失效
标题翻译：具有持续“锁获取”状态的扩展缓存一致性协议
公开(公告)号：US06629214B1
公开(公告)日：2003-09-30
申请号：US09437186
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1300
CPC分类号： G06F12/0815 , G06F9/3004 , G06F9/30087 , G06F9/3857
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized. In particular, the claimed system and method provides that a given processor, after acquiring a lock or reservation to a given cache line, will keep the lock, to make successive modifications to the cache line, instead of releasing it to other processors after making only one modification. By doing so, the overhead typically required to acquire a lock before making any cache line modification is eliminated for successive modifications.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的传统系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的缓存状态允许优化缓存状态转换序列。特别地，所要求保护的系统和方法规定，给定的处理器在获得对给定高速缓存行的锁定或预留之后将保持锁定以对缓存行进行连续修改，而不是在仅进行制作之后将其释放到其他处理器一个修改。通过这样做，为了连续修改，消除了在进行任何高速缓存行修改之前获取锁的通常需要的开销。

3. 发明授权

US06345344B1 Cache allocation mechanism for modified-unsolicited cache state that modifies victimization priority bits 失效
标题翻译：修改未经请求的缓存状态的缓存分配机制，修改受害优先级位
公开(公告)号：US06345344B1
公开(公告)日：2002-02-05
申请号：US09437181
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in 5 a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改后的未经请求（Mu）高速缓存状态，以指示缓存行5中保存的值已经被修改（即当前与系统存储器不一致），但是被另一个处理单元修改通过与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用Mu状态。读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

4. 发明授权

US06629212B1 High speed lock acquisition mechanism with time parameterized cache coherency states 有权
标题翻译：具有时间参数化高速缓存一致性状态的高速锁定采集机制
公开(公告)号：US06629212B1
公开(公告)日：2003-09-30
申请号：US09437187
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently “bounce” between multiple processors, which causes a significant reduction in cache efficiency. The preferred embodiment provides a modified MESI state which holds the status of the cache line static for a fixed period of time, which eliminates the bounce effect from contention between multiple processors.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。在使用MESI方法的常规系统中，两个或多个处理器通常将竞争公用高速缓存行的所有权。因此，高速缓存行的所有权将在多个处理器之间频繁地“反弹”，这导致高速缓存效率的显着降低。优选实施例提供修改的MESI状态，其将高速缓存行的状态保持固定的固定时间段，从而消除了来自多个处理器之间的争用的反弹效应。

5. 发明授权

US06549989B1 Extended cache coherency protocol with a “lock released” state 失效
标题翻译：具有“锁定释放”状态的扩展缓存一致性协议
公开(公告)号：US06549989B1
公开(公告)日：2003-04-15
申请号：US09437184
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。优选实施例提供了附加高速缓存状态，其特别地指示处理器在执行任何必要的修改之后已经在高速缓存线上释放其锁定。

6. 发明授权

US06349369B1 Protocol for transferring modified-unsolicited state during data intervention 有权
标题翻译：缓存一致性协议，提供来自中间缓存的标志，以指示修改的高速缓存行的释放
公开(公告)号：US06349369B1
公开(公告)日：2002-02-19
申请号：US09437180
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（MU）高速缓存状态，以指示保持在高速缓存行中的值已被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含MU状态的值的高速缓存相关联的处理单元，并且该值被保持为任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用MU状态。读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

7. 发明授权

US06314498B1 Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache 失效
标题翻译：多处理器系统总线事务，用于将独占解除缓存状态转移到低级缓存
公开(公告)号：US06314498B1
公开(公告)日：2001-11-06
申请号：US09437197
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译：高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值的计算机系统。如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

8. 发明授权

US06629209B1 Cache coherency protocol permitting sharing of a locked data granule 失效
标题翻译：缓存一致性协议允许共享锁定的数据粒子
公开(公告)号：US06629209B1
公开(公告)日：2003-09-30
申请号：US09437185
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

9. 发明授权

US06625701B1 Extended cache coherency protocol with a modified store instruction lock release indicator 失效
标题翻译：扩展缓存一致性协议，具有修改后的存储指令锁定释放指示器
公开(公告)号：US06625701B1
公开(公告)日：2003-09-23
申请号：US09437183
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1214
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

10. 发明授权

US06345342B1 Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line 有权
标题翻译：缓存一致性协议采用包括可编程标志的读取操作来指示干预的高速缓存行的解除分配
公开(公告)号：US06345342B1
公开(公告)日：2002-02-05
申请号：US09437177
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
摘要翻译：一种新颖的高速缓存一致性协议提供修改的非请求（Mu）高速缓存状态，以指示保持在高速缓存行中的值已经被修改（即，当前不符合系统存储器），但是被另一个处理单元修改，而不是由与当前包含Mu状态的值的高速缓存相关联的处理单元，并且该值被保持为排除任何其他水平相邻的高速缓存。因为该值是唯一保留的，所以可以在该高速缓存中修改该值，而不需要向存储器层级中的其他水平高速缓存发出总线事务。作为对读取请求的窥探响应的结果，可以应用Mu状态。读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。或者，可以向标记提供干预数据，以指示请求的高速缓存应该利用修改的未经请求的状态。

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