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1. 发明授权

US06587924B2 Scarfing within a hierarchical memory architecture 有权
标题翻译：在分层内存架构中进行扫描
公开(公告)号：US06587924B2
公开(公告)日：2003-07-01
申请号：US09903727
申请日：2001-07-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y10S707/99931
摘要： A method and system for scarfing data during a data access transaction within a hierarchical data storage system. A data access request is delivered from a source device to a plurality of data storage devices. The access request includes a target address and a source path tag, wherein the source path tag includes a device identification tag that uniquely identifies a data storage device within a given level of the system traversed by the access request. A device identification tag that uniquely identifies the third party transactor within a given memory level is appended to the source path tag such that the third party transactor can scarf returning data without reserving a scarf queue entry.
摘要翻译：一种用于在分层数据存储系统内的数据访问事务期间对数据进行分页的方法和系统。数据访问请求从源设备传送到多个数据存储设备。访问请求包括目标地址和源路径标签，其中源路径标签包括唯一地标识由访问请求遍历的系统的给定级别内的数据存储设备的设备标识标签。唯一地标识给定存储器级别内的第三方交易者的设备识别标签被附加到源路径标签，使得第三方交易者可以围绕返回数据而不预留围巾队列条目。

2. 发明授权

US06505277B1 Method for just-in-time delivery of load data by intervening caches 失效
标题翻译：通过插入缓存来及时传送负载数据的方法
公开(公告)号：US06505277B1
公开(公告)日：2003-01-07
申请号：US09344057
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0806 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F12/0811 , G06F12/0859
摘要： A method for ordering the time of issue of a load instruction from a lower level (L2) intervening cache, interlinked by a system bus to a first L2 cache. The method comprises the steps of (i) appending a cycle of dependency (CoD) value to said load instruction, where the CoD value corresponds to a specified time, measured in cycles, on a synchronized timer (ST) at which the data is required by a downstream dependency, (ii) monitoring when a search of the first cache by said load instruction results in a miss, (iii) searching the load instruction at the second cache when the miss is detected, and (iv) providing the data requested by the load instruction from the intervening cache to a pipeline of a system resource of said first L2 cache at the specified time.
摘要翻译：一种用于从由下一级（L2）中间缓存发出加载指令的时间的方法，该系统总线与第一L2高速缓存相互连接。该方法包括以下步骤：（i）将附加循环（CoD）值附加到所述加载指令，其中CoD值对应于在需要数据的同步定时器（ST）上以周期测量的指定时间通过下游依赖性，（ii）监视当所述加载指令对第一高速缓存的搜索导致错过时，（iii）在检测到未命中时搜索第二高速缓存上的加载指令，以及（iv）提供所请求的数据通过在指定时间从中间缓存到所述第一L2高速缓存的系统资源的流水线的加载指令。

3. 发明授权

US06477613B1 Cache index based system address bus 有权
标题翻译：基于缓存索引的系统地址总线
公开(公告)号：US06477613B1
公开(公告)日：2002-11-05
申请号：US09345302
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897
摘要： Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin directory lookups in lower level storage devices before the address tag is received. The remainder of the address is transmitted during subsequent bus cycles, which should be in time for address tag comparisons with the congruence class elements. To allow multiple directory lookups to be occurring concurrently in a pipelined directory, a portion of multiple addresses for several data access operations, each portion including the index field for the respective address, may be transmitted during the first bus cycle or staged in consecutive bus cycles, with the remainders of each address—including the cache tags—transmitted during the subsequent bus cycles. This allows directory lookups utilizing the index fields to be processed concurrently within a lower level storage device for multiple operations, with the address tags being provided later, but still timely for tag comparisons at the end of the directory lookup. Where the lower level storage device operates at a higher frequency than the bus, overall latency is reduced and directory bandwidth is more efficiently utilized.
摘要翻译：在操作的高速缓存未命中之后，操作的地址在将高速缓存耦合到存储层级的较低级别的总线上传输。包括索引字段的地址的一部分在第一总线周期期间被发送，并且可以用于在接收到地址标签之前开始下级存储设备中的目录查找。在随后的总线周期期间传送地址的其余部分，这些时间应与地址标签与同余类元素进行比较。为了允许在流水线目录中同时发生多个目录查找，可以在第一个总线周期期间发送多个数据访问操作的多个地址的一部分，每个部分包括相应地址的索引字段，或者在连续的总线周期中分段，每个地址的剩余部分，包括在后续总线周期期间发送的缓存标签。这允许使用索引字段的目录查找在较低级存储设备中同时处理以用于多个操作，其中地址标签稍后提供，但是在目录查找结束时仍然适合于标签比较。在较低级存储设备以比总线更高的频率工作的地方，总体延迟降低，目录带宽更有效地利用。

4. 发明授权

US06374330B1 Cache-coherency protocol with upstream undefined state 失效
标题翻译：具有上行未定义状态的缓存一致性协议
公开(公告)号：US06374330B1
公开(公告)日：2002-04-16
申请号：US08839545
申请日：1997-04-14
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0831
摘要： A method of maintaining cache-coherency in a multi-processor computer system provides new states to indicate that a sector in an upstream cache has been modified, without executing unnecessary bus transactions for the lower-level cache(s). These new “U” states can indicate which sector in the cache line was modified, or if the cache line was the subject of a cachable write-through operation. The protocol is implemented as an improvement to the prior-art “MESI” cache-coherency protocol. The new protocol is especially useful in handling allocate-and-zero instructions wherein data is modified in the cache (zeroed out) without first fetching the old data from memory. In the embodiment wherein there are only two sectors in a given cache line, three new states are provided to indicate which sector was modified, or whether any cachable write-through operation was performed on the cache line of the first-level cache.
摘要翻译：在多处理器计算机系统中维持高速缓存一致性的方法提供新状态以指示上游缓存中的扇区已被修改，而不对下级缓存执行不必要的总线事务。这些新的“U”状态可以指示高速缓存行中的哪个扇区被修改，或者高速缓存行是高速缓存直写操作的主题。该协议被实现为对现有技术的“MESI”高速缓存一致性协议的改进。新协议在处理分配和零指令时特别有用，其中数据在缓存中被修改（清零），而无需先从存储器中取出旧数据。在给定高速缓存行中只有两个扇区的实施例中，提供了三个新状态来指示哪个扇区被修改，或者是否在第一级高速缓存的高速缓存行上执行了任何可高速缓存的直写操作。

5. 发明授权

US06343344B1 System bus directory snooping mechanism for read/castout (RCO) address transaction 失效
标题翻译：系统总线事务与缓存标签的受害者地址
公开(公告)号：US06343344B1
公开(公告)日：2002-01-29
申请号：US09368221
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0859
摘要： In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.
摘要翻译：响应于接收到用于相关数据访问和丢弃操作的组合地址，包括标识包含数据访问目标和丢弃的受害者的同余类的索引，使用索引来定位单个目录访问一致类。然后将同余类中的地址标签与用于数据访问操作的地址标签和用于外推操作的地址标签同时进行比较，并酌情生成单独的命中信号。然而，仅需要单个目录访问，而不是如已知技术中所需的两个单独的目录访问，利用数据访问目标和丢弃的受害者都属于单个同余类的事实。响应延迟也得到改善，地址总线带宽利用率也得到提高。

6. 发明授权

US06341336B1 Cache coherency protocol having tagged state used with cross-bars 失效
标题翻译：具有标记状态的缓存一致性协议与交叉条使用
公开(公告)号：US06341336B1
公开(公告)日：2002-01-22
申请号：US09024676
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1214
CPC分类号： G06F12/0833
摘要： A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.
摘要翻译：高速缓存一致性协议使用“标记”一致性状态跟踪将修改后的值写回系统内存的责任，允许干预该值而不会立即将其写回系统内存，从而增加内存带宽。当分配给最近加载修改值的高速缓存行时，Tagged状态可以跨缓存迁移（水平）。与Tagged状态有关的历史状态可能会被进一步使用。本发明还可以应用于具有群集处理单元的多处理器计算机系统，使得标签状态可以应用于支持单独处理单元群集的每组高速缓存中的一个高速缓存行。优先级被分配给不同的缓存状态，包括标签状态，用于响应访问对应的存储器块的请求。任何标记的干预响应只能转发到可能受到干预响应影响的所选高速缓存，使用交叉条。标签协议可以与现有的和新的高速缓存一致性协议相结合。本发明进一步考虑使用标签状态对高速缓存操作的独立优化。

7. 发明授权

US06334172B1 Cache coherency protocol with tagged state for modified values 失效
标题翻译：缓存一致性协议，具有修改值的带状态
公开(公告)号：US06334172B1
公开(公告)日：2001-12-25
申请号：US09024393
申请日：1998-02-17
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0815
摘要： A cache coherency protocol uses a “Tagged” coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.
摘要翻译：高速缓存一致性协议使用“标记”一致性状态跟踪将修改后的值写回系统内存的责任，允许干预该值而不会立即将其写回系统内存，从而增加内存带宽。当分配给最近加载修改值的高速缓存行时，Tagged状态可以跨缓存迁移（水平）。与Tagged状态有关的历史状态可能会被进一步使用。本发明还可以应用于具有群集处理单元的多处理器计算机系统，使得标签状态可以应用于支持单独处理单元群集的每组高速缓存中的一个高速缓存行。优先级被分配给不同的缓存状态，包括标签状态，用于响应访问对应的存储器块的请求。任何标记的干预响应只能转发到可能受到干预响应影响的所选高速缓存，使用交叉条。标签协议可以与现有的和新的高速缓存一致性协议相结合。本发明进一步考虑使用标签状态对高速缓存操作的独立优化。

8. 发明授权

US06324617B1 Method and system for communicating tags of data access target and castout victim in a single data transfer 失效
标题翻译：用于在单个数据传输中传送数据访问目标和丢弃受害者的标签的方法和系统
公开(公告)号：US06324617B1
公开(公告)日：2001-11-27
申请号：US09368222
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0859
摘要： A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
摘要翻译：组合的地址总线事务包含用于数据访问操作目标的地址标签，要替换的受害者的地址标签，以及标识包括目标和受害者的一致类的地址索引字段。目的地状态信息，例如用于投放受害者的一致性状态和/或LRU位置也可以附加到总线操作中的索引字段和目标和受害者地址标签。从而改善了地址总线带宽利用率，消除了根据现有实践分离数据访问和丢弃操作所采用的索引字段的重复传输。可以同时确定受害者是否可以在形成组合地址的存储设备内找到目标，从而提高该设备的整体性能。

9. 发明授权

US6157980A Cache directory addressing scheme for variable cache sizes 失效
标题翻译：用于可变缓存大小的缓存目录寻址方案
公开(公告)号：US6157980A
公开(公告)日：2000-12-05
申请号：US46016
申请日：1998-03-23
申请人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Jerry Don Lewis
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0864
摘要： To avoid multiplexing within the critical address path, the same field from an address is employed to index rows within a cache directory and memory regardless of the size of the cache memory. Depending on the size of the cache memory being employed, different address bits (such as Add[12] or Add[25] are employed as a "late select" for the last stage of multiplexing within the cache directory and cache memory. Since smaller address tag fields are employed for the larger cache memory size, the extra address tag bit is forced to a logic 1 within the cache directory and compared to a logic 1 by address tag comparators at the output of the cache directory.
摘要翻译：为了避免在关键地址路径中进行多路复用，来自地址的相同字段用于对高速缓存目录和存储器内的行进行索引，而与高速缓冲存储器的大小无关。根据所使用的高速缓冲存储器的大小，不同的地址位（例如Add [12]或Add [25]）被用作高速缓存目录和高速缓冲存储器内的最后一个复用阶段的“晚期选择” 地址标签字段用于较大的高速缓存存储器大小，额外地址标签位被强制为高速缓存目录内的逻辑1，并与高速缓存目录的输出处的地址标签比较器与逻辑1进行比较。

10. 发明授权

US06112270A Method and system for high speed transferring of strictly ordered bus operations by reissuing bus operations in a multiprocessor system 失效
标题翻译：通过在多处理器系统中重新发布总线操作，高速传输严格有序的总线操作的方法和系统
公开(公告)号：US06112270A
公开(公告)日：2000-08-29
申请号：US833227
申请日：1997-10-31
申请人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
发明人： Jerry Don Lewis , John Steven Dodson , Ravi Kumar Arimilli
IPC分类号： G06F13/36 , G06F13/00
CPC分类号： G06F13/36
摘要： A system and method for high speed transferring of bus operations which are preferably strictly ordered in a processing system is provided. A system and method in accordance with the present invention comprises issuing a plurality of bus operation requests by a processor and determining if a first response has been received by the same processor indicating that one of the plurality of bus operation requests should be reissued. Then, if the first response is received, the processor provides a second response indicating that at least another of the issued bus operation requests should be reissued.
摘要翻译：提供了优选地在处理系统中严格排序的总线操作的高速传输的系统和方法。根据本发明的系统和方法包括：由处理器发出多个总线操作请求，并确定是否已经由同一个处理器接收到指示应该重新发出多个总线操作请求之一的第一响应。然后，如果接收到第一响应，则处理器提供第二响应，指示应该重发发出的总线操作请求中的至少另一个。

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