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1. 发明授权

US4717591A Prevention of mechanical and electronic failures in heat-treated structures 失效
标题翻译：预防热处理结构中的机械和电子故障
公开(公告)号：US4717591A
公开(公告)日：1988-01-05
申请号：US836781
申请日：1986-03-06
申请人： Raul E. Acosta , Wilma J. Horkans , Ruby Mukherjee , Judith D. Olsen
发明人： Raul E. Acosta , Wilma J. Horkans , Ruby Mukherjee , Judith D. Olsen
IPC分类号： C23C30/00 , H05K3/24 , H05K3/38 , H05K3/46 , C23C18/36
CPC分类号： H05K3/244 , C23C30/00 , H05K3/384 , H05K2203/072 , H05K3/4644
摘要： This invention relates to the prevention of mechanical and electrical failures in structures that are heat-treated, and more particularly relates to the use of coating layers containing Co and P on corrosible materials such as Cu. The invention has significant utility in the protection of Cu current-carrying lines in electronic structures that comprise multi layers that are subjected to heat treatments that would normally adversely affect the Cu lines. The CoP coating layer also acts to prevent interdiffusion between Cu and contact metals, such as Au.
摘要翻译：本发明涉及防止被热处理的结构中的机械和电气故障，更具体地说，涉及在诸如Cu之类的腐蚀性材料上含有Co和P的涂层。本发明在电子结构中的Cu载流线路的保护方面具有显着的用途，其包括经受热处理的多层，其通常不利地影响Cu线。 CoP涂层还起到防止Cu和金属（例如Au）之间的相互扩散的作用。

2. 发明授权

US06720230B2 Method of fabricating integrated coil inductors for IC devices 有权
标题翻译： IC器件集成线圈电感器的制造方法
公开(公告)号：US06720230B2
公开(公告)日：2004-04-13
申请号：US10238746
申请日：2002-09-10
申请人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
发明人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01F17/0006 , H01F17/0033 , H01F41/041 , H01L27/08
摘要： A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.
摘要翻译：提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。线圈的非嵌入部分被制造为BEOL金属化层的一部分。这允许螺线管的大的横截面积的匝数，从而减少匝间电容耦合。由于本发明的螺线管线圈具有大直径的横截面，所以线圈可以制造成具有大的电感值，并且占据芯片的小面积。所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔，然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。在平坦化之后，螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分（即，作为BEOL的线/通路）。为了进一步增加螺线管线圈的横截面，可以通过电沉积通过BEOL层顶部的掩模来构建。

3. 发明授权

US5793836A X-ray mask pellicle 失效
标题翻译： X射线面具防护薄膜
公开(公告)号：US5793836A
公开(公告)日：1998-08-11
申请号：US716657
申请日：1996-09-06
申请人： Juan R. Maldonado , Raul E. Acosta , Marie Angelopoulos , Fuad E. Doany , Chandrasekhar Narayan , Andrew T. S. Pomerene , Jane M. Shaw , Kurt R. Kimmel
发明人： Juan R. Maldonado , Raul E. Acosta , Marie Angelopoulos , Fuad E. Doany , Chandrasekhar Narayan , Andrew T. S. Pomerene , Jane M. Shaw , Kurt R. Kimmel
IPC分类号： G03F1/00 , G03F1/22 , G03F1/62 , G03F1/64 , G03F7/20 , H01L21/027 , H05K1/00
CPC分类号： G03F1/62 , G03F1/22 , G03F1/64 , G03F7/70691
摘要： An X-ray mask pellicle is capable of protecting the X-ray mask from contaminants and the wafer from contact with the X-ray absorber material of the mask. The X-ray mask pellicle is sufficiently thin to allow X-ray exposure at the required mask to wafer gaps yet is sufficiently durable, replaceable, tough and X-ray resistant to be used in X-ray lithography. A thin (organic or inorganic) X-ray mask pellicle to be placed covering the X-ray mask pattern area is fabricated as a thin film and attached to a support ring. A selected area of the pellicle film, tailored to cover the absorber pattern in the X-ray mask, is etched to decrease its thickness to below 2 .mu.m. If the thin film of the pellicle is not itself conductive, a thin conductive film may be coated on both sides. In an alternative embodiment, the separation between the pellicle and the X-ray mask can be achieved by forming the mask with a stepped profile.
摘要翻译： X射线掩模防护薄膜组件能够保护X射线掩模免受污染物和晶片与掩模的X射线吸收材料的接触。 X射线掩模防护薄膜是足够薄的，以允许所需掩模的X射线暴露于晶片间隙，而且在X射线光刻中使用的是足够耐用的，可更换的，坚固的和耐X射线的。将覆盖X射线掩模图案区域的薄（有机或无机）X射线掩模防护薄膜组件制成薄膜并附着在支撑环上。为了覆盖X射线掩模中的吸收体图案而定制的防护薄膜的选定区域被蚀刻以将其厚度减小到低于2μm。如果防护薄膜的薄膜本身不是导电的，则可以在两侧涂覆薄导电膜。在替代实施例中，防护薄膜组件和X射线掩模之间的分离可以通过以阶梯轮廓形成掩模来实现。

4. 发明授权

US06639488B2 MEMS RF switch with low actuation voltage 有权
标题翻译：具有低致动电压的MEMS RF开关
公开(公告)号：US06639488B2
公开(公告)日：2003-10-28
申请号：US09948478
申请日：2001-09-07
申请人： Hariklia Deligianni , Robert Groves , Christopher Jahnes , Jennifer L. Lund , Panayotis Andricacos , John Cotte , L. Paivikki Buchwalter , David Seeger , Raul E. Acosta
发明人： Hariklia Deligianni , Robert Groves , Christopher Jahnes , Jennifer L. Lund , Panayotis Andricacos , John Cotte , L. Paivikki Buchwalter , David Seeger , Raul E. Acosta
IPC分类号： H01P110
CPC分类号： H01P1/12 , H01H59/0009 , H01H2059/0036
摘要： Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to ground. The lower electrode transmits the RF signal when the top beam or beams are up and when the upper beams are actuated and bent down, the transmission line is shunted to ground ending the RF transmission. A high dielectric constant material is used in the capacitive portion of the switch to achieve a high capacitance per unit area thus reducing the required chip area and enhancing the insertion loss characteristics in the non-actuated state. A gap between beam and lower electrode of less than 1 &mgr;m is incorporated in order to minimize the electrostatic potential (pull-in voltage) required to actuate the switch.
摘要翻译：公开了一种电容静电MEMS RF开关，其由作为传输线和致动电极两者的下电极组成。此外，在下电极上方有一个或多个连接到地面的固定梁的阵列。当顶部梁或梁向上时，下部电极发射RF信号，并且当上部梁被致动并向下弯曲时，传输线被分流到结束RF传输的地面。在开关的电容部分中使用高介电常数材料以实现每单位面积的高电容，从而在非致动状态下减少所需的芯片面积并增强插入损耗特性。引入小于1um的光束和下电极之间的间隙以便使致动开关所需的静电电位（拉入电压）最小化。

5. 发明授权

US4479980A Plating rate monitor 失效
标题翻译：电镀速率监视器
公开(公告)号：US4479980A
公开(公告)日：1984-10-30
申请号：US562390
申请日：1983-12-16
申请人： Raul E. Acosta , Edward J. Yarmchuk
发明人： Raul E. Acosta , Edward J. Yarmchuk
IPC分类号： H05K3/18 , C23C18/16 , C23C18/31 , C23C18/40 , G01B7/06 , H05K1/02 , H05K3/00 , H05K3/24 , C23C3/00 , C23C3/02
CPC分类号： G01B7/06 , H05K1/0266 , H05K3/187 , H05K3/241
摘要： A plating rate monitor includes a Wheatstone bridge, one branch of which is a monitoring resistor formed on a printed circuit board located in the same environment as an object being plated. The resistor undergoes plating at the same rate as the object. Each time the bridge becomes balanced, another resistor branch of the bridge, which is variable, is incremented by a preselected value to upset the balance. As the monitoring resistor in the plating environment undergoes plating, a change in its resistance causes the bridge to become balanced once again and the time interval for achieving this balance, for a calculated plating thickness change of the monitoring resistor, determines the plating rate.
摘要翻译：电镀速率监视器包括惠斯登电桥，其一个分支是形成在与被电镀的对象相同的环境中的印刷电路板上形成的监视电阻。电阻器以与物体相同的速率进行电镀。每当桥变得平衡时，桥的另一个电阻分支是可变的，增加一个预选的值来扰乱天平。由于电镀环境中的监测电阻器经受电镀，其电阻变化使得桥接器再次平衡，并且为了实现该平衡的时间间隔，对于监测电阻器的计算电镀厚度变化，确定电镀速率。

6. 发明授权

US06534843B2 High Q inductor with faraday shield and dielectric well buried in substrate 有权
公开(公告)号：US06534843B2
公开(公告)日：2003-03-18
申请号：US09781014
申请日：2001-02-10
申请人： Raul E. Acosta , Jennifer L. Lund , Robert A. Groves , Joanna Rosner , Steven A. Cordes , Melanie L. Carasso
发明人： Raul E. Acosta , Jennifer L. Lund , Robert A. Groves , Joanna Rosner , Steven A. Cordes , Melanie L. Carasso
IPC分类号： H01L2900
CPC分类号： H01F17/0006 , H01F27/362
摘要： Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

7. 发明授权

US06492708B2 Integrated coil inductors for IC devices 有权
标题翻译：用于IC器件的集成线圈电感器
公开(公告)号：US06492708B2
公开(公告)日：2002-12-10
申请号：US09808381
申请日：2001-03-14
申请人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
发明人： Raul E. Acosta , Melanie L. Carasso , Steven A. Cordes , Robert A. Groves , Jennifer L. Lund , Joanna Rosner
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01F17/0006 , H01F17/0033 , H01F41/041 , H01L27/08
摘要： A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP. After planarization the fabrication of the remaining part of the solenoidal coil is fabricated as part of the metallization in the BEOL (i.e. as line/vias of the BEOL). To further increase the cross section of the solenoidal coil part of it may be built by electrodeposition through a mask on top of the BEOL layers.
摘要翻译：提供一种用于制造集成在半导体芯片中的螺线管电感器的装置。螺线管线圈部分地嵌入到蚀刻到芯片衬底中的深阱中。线圈的非嵌入部分被制造为BEOL金属化层的一部分。这允许螺线管的大的横截面积的匝数，从而减少匝间电容耦合。由于本发明的螺线管线圈具有大直径的横截面，所以线圈可以制造成具有大的电感值，并且占据芯片的小面积。所述制造工艺包括在所有FEOL步骤完成之后蚀刻衬底中的深空腔; 用电介质衬里所述空腔，然后制造将通过掩模沉积导电材料金属而嵌入的线圈部分; 通过CMP沉积其相同的电介质和平面化。在平坦化之后，螺线管线圈的剩余部分的制造被制造为BEOL中的金属化的一部分（即，作为BEOL的线/通路）。为了进一步增加螺线管线圈的横截面，可以通过电沉积通过BEOL层顶部的掩模来构建。

8. 发明授权

US06762088B2 High Q inductor with faraday shield and dielectric well buried in substrate 有权
标题翻译：高Q电感与法拉第屏蔽和电介质井埋在基板中
公开(公告)号：US06762088B2
公开(公告)日：2004-07-13
申请号：US10336291
申请日：2003-01-03
申请人： Raul E. Acosta , Jennifer L. Lund , Robert A. Groves , Joanna Rosner , Steven A. Cordes , Melanie L. Carasso
发明人： Raul E. Acosta , Jennifer L. Lund , Robert A. Groves , Joanna Rosner , Steven A. Cordes , Melanie L. Carasso
IPC分类号： H01L2120
CPC分类号： H01F17/0006 , H01F27/362
摘要： Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.
摘要翻译：通过将阱蚀刻到衬底中直到覆盖衬底的绝缘层并且在阱的底部中形成细长段的形式的接地法拉第屏蔽，在IC结构中消除了对半导体衬底的电感器损耗。阱位于电感器的正下方，并且可选地填充有固化的低k有机电介质或空气。

9. 发明授权

US5958631A X-ray mask structure 失效
标题翻译： X光掩模结构
公开(公告)号：US5958631A
公开(公告)日：1999-09-28
申请号：US24087
申请日：1998-02-17
申请人： Raul E. Acosta , Juan R. Maldonado
发明人： Raul E. Acosta , Juan R. Maldonado
IPC分类号： G03F1/22 , G03F1/62 , H01L21/027 , G03F9/00
CPC分类号： G03F1/22 , G03F1/62
摘要： A universal mask for use in making Integrated Circuits. The individual size masks are produced on a wafer having standardized, large size membrane area. A combined X-ray blocking and membrane stiffening layer is applied on at least one side of the wafer. This stiffening/blocking layer includes an X-ray transparent region having a size commensurate with the desired exposure field and aligned therewith.
摘要翻译：用于制造集成电路的通用掩模。单个尺寸的掩模在具有标准化的大尺寸膜面积的晶片上产生。将组合的X射线遮挡和膜加强层施加在晶片的至少一侧上。该加强/阻挡层包括具有与期望的曝光场相当的尺寸并与之对准的X射线透明区域。

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