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1. 发明授权

US5636130A Method of determining signal propagation delay through circuit elements 失效
标题翻译：通过电路元件确定信号传播延迟的方法
公开(公告)号：US5636130A
公开(公告)日：1997-06-03
申请号：US498338
申请日：1995-07-05
申请人： Raoul B. Salem , Vernon R. Brethour , Wen-Jay Hsu , Raymond A. Heald , Subramanian Ganesan
发明人： Raoul B. Salem , Vernon R. Brethour , Wen-Jay Hsu , Raymond A. Heald , Subramanian Ganesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method is provided for accurately determining the propagation delay of a gate under consideration in a static timing analyzer. This is accomplished by determining both the output load and input rise time of the gate under consideration. These values are then compared with a load versus rise time grid having previously determined values of propagation delay (points) for specified combinations of load and input rise time. These points are then used to interpolate a value of propagation delay for the gate under consideration by an interpolation technique that accounts for at least one of the following non-linear effects: the feed forward capacitance of a gate, soft switching, gate resistance, source and drain resistance, and/or other non-linear effects. The method accounts for each non-linear effect by imparting a corresponding component to propagation delay only in that range of output load and input rise time for which that non-linear effect is most pronounced.
摘要翻译：提供了一种用于在静态定时分析器中精确地确定考虑的门的传播延迟的方法。这是通过确定所考虑的门的输出负载和输入上升时间来实现的。然后将这些值与具有先前确定的负载和输入上升时间的组合的传播延迟（点）值的负载对上升时间网格进行比较。这些点然后用于通过考虑以下非线性效应中的至少一个的内插技术来内插所考虑的门的传播延迟的值：栅极的前馈电容，软开关，栅极电阻，源极和漏极电阻，和/或其他非线性效应。该方法通过仅在该输出负载的范围和非线性效应最显着的输入上升时间赋予相应的分量来传播每个非线性效应。

2. 发明授权

US6140856A Parametric tuning of an intergrated circuit after fabrication 失效
公开(公告)号：US6140856A
公开(公告)日：2000-10-31
申请号：US956624
申请日：1997-09-11
申请人： Sathyanandan Rajivan , Raoul B. Salem
发明人： Sathyanandan Rajivan , Raoul B. Salem
IPC分类号： H03K19/0175 , G01R31/30 , G01R31/317 , H03K5/00 , H03K19/00 , H03K19/0185 , H03K19/0948 , H03K19/173 , H03H11/26
CPC分类号： G01R31/30 , H03K19/0005 , H03K19/0027 , H03K19/018585 , H03K19/1731 , G01R31/31702 , H03K2005/00071
摘要： The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

3. 发明授权

US5930094A Cascoded-MOS ESD protection circuits for mixed voltage chips 有权
标题翻译：用于混合电压芯片的Cascoded-MOS ESD保护电路
公开(公告)号：US5930094A
公开(公告)日：1999-07-27
申请号：US140051
申请日：1998-08-26
申请人： E. Ajith Amerasekera , Raoul B. Salem
发明人： E. Ajith Amerasekera , Raoul B. Salem
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H02H9/04
CPC分类号： H01L27/0251 , H01L27/0266
摘要： Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.
摘要翻译：限定了串联nMOS ESD保护电路中的控制端电压的偏置电路，使得在正常工作期间电路处于高阻态（OFF），并且在ESD事件期间具有低阻抗（ON）。 G1和G2是在焊盘的ESD事件期间定义V3和V4的驱动电路。在正常工作期间，V3和/或V4为高电平，焊盘和VSS之间没有电流流动。在ESD事件期间，V3和V4为高电平，两个器件在外部NPN导通时会导通MOS电流。二极管D1导通电流Cc，芯片电容，提高VDD，使G1和G2导通，并将V3和V4升高到大于nMOS阈值电压的电平。

4. 发明授权

US5973541A Parametric tuning of an integrated circuit after fabrication 失效
公开(公告)号：US5973541A
公开(公告)日：1999-10-26
申请号：US927976
申请日：1997-09-11
申请人： Sathyanandan Rajivan , Raoul B. Salem
发明人： Sathyanandan Rajivan , Raoul B. Salem
IPC分类号： H03K19/0175 , G01R31/30 , G01R31/317 , H03K5/00 , H03K19/00 , H03K19/0185 , H03K19/0948 , H03K19/173 , H03K17/04
CPC分类号： G01R31/30 , H03K19/0005 , H03K19/0027 , H03K19/018585 , H03K19/1731 , G01R31/31702 , H03K2005/00071
摘要： The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

5. 发明授权

US5729158A Parametric tuning of an integrated circuit after fabrication 失效
公开(公告)号：US5729158A
公开(公告)日：1998-03-17
申请号：US499716
申请日：1995-07-07
申请人： Sathyanandan Rajivan , Raoul B. Salem
发明人： Sathyanandan Rajivan , Raoul B. Salem
IPC分类号： H03K19/0175 , G01R31/30 , G01R31/317 , H03K5/00 , H03K19/00 , H03K19/0185 , H03K19/0948 , H03K19/173
CPC分类号： G01R31/30 , H03K19/0005 , H03K19/0027 , H03K19/018585 , H03K19/1731 , G01R31/31702 , H03K2005/00071
摘要： The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

6. 发明授权

US4385323A Camera pickup tube circuit for automatically suppressing excessive highlights in response to their occurrence 失效
标题翻译：相机拾取管电路，用于自动抑制超出亮度的响应
公开(公告)号：US4385323A
公开(公告)日：1983-05-24
申请号：US802839
申请日：1977-06-02
申请人： Raoul B. Salem , Vinson R. Perry
发明人： Raoul B. Salem , Vinson R. Perry
IPC分类号： H04N5/228 , H04N5/30
CPC分类号： H04N5/2286
摘要： A circuit for suppressing the effects of excessive highlights is automatically enabled in response to highlights in the viewed scene which exceed a given threshold. The circuit is used in combination with a special pickup tube or tubes which include excessive highlight protection elements and a corresponding mode of operation. The circuit allows the continuous operation of the pickup tubes with improved resolution at a heretofore prohibitive, but preferred, high voltage level (e.g., 950 volts), rather than the generally accepted and recommended operating level (e.g., 750 volts) therefor, while prolonging the lifetime of such tubes. Detector means generates the circuit enable signal in response to the presence of highlights in excess of the given threshold. Control circuit means are conditioned thereby to drive the tube into the corresponding mode of operation during the line flyback period corresponding to the horizontal blanking interval.
摘要翻译：响应于超过给定阈值的观看场景中的高光，自动启用用于抑制过高亮度的影响的电路。该电路与特殊的拾取管或管组合使用，其包括过多的高亮保护元件和相应的操作模式。该电路允许以迄今禁止但优选的高电压电平（例如，950伏特）的改进的分辨率连续操作拾取管，而不是通常接受和推荐的操作电平（例如，750伏），同时延长这种管的寿命。检测器装置响应超过给定阈值的亮度的存在而产生电路使能信号。控制电路装置被调节，从而在对应于水平消隐间隔的行回扫时段期间将管驱动到相应的操作模式。

7. 发明授权

US06300677B1 Electronic assembly having improved power supply bus voltage integrity 失效
标题翻译：电子组件具有改进的电源总线电压完整性
公开(公告)号：US06300677B1
公开(公告)日：2001-10-09
申请号：US09387280
申请日：1999-08-31
申请人： Raoul B. Salem
发明人： Raoul B. Salem
IPC分类号： H01L2352
CPC分类号： H01L25/16 , H01L23/5386 , H01L2224/16 , H01L2224/16227 , H01L2224/16265 , H01L2924/15159 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/19103 , H01L2924/19104 , H01L2924/19105
摘要： An electronic assembly is described herein having a first semiconductor integrated circuit substrate with circuitry disposed thereon. This semiconductor integrated circuit substrate is coupled with a package through a first plurality of electrical connections. Sandwiched between portions of the semiconductor integrated circuit substrate and the package is an electronic assembly which is coupled to the semiconductor substrate circuitry and also the package through low resistance, low inductance connections. An electronic subassembly is described which includes a second semiconductor substrate having circuitry disposed thereon, the circuitry forming one or more of a capacitor, a charge pump, or a voltage regulator. Insulating material is disposed over the circuitry, and vias are formed therethrough. Metal bands are disposed to be continuous around the outside of the subassembly, thereby also forming a connection with the second semiconductor circuitry. The electronic subassembly metal bands then make connections with the circuitry of the semiconductor integrated circuit substrate and the package.
摘要翻译：本文描述的电子组件具有其上设置有电路的第一半导体集成电路基板。该半导体集成电路衬底通过第一多个电连接与封装耦合。在半导体集成电路基板和封装的部分之间夹入的是电子组件，其通过低电阻，低电感连接耦合到半导体衬底电路以及封装。描述了一种电子子组件，其包括其上设置有电路的第二半导体衬底，该电路形成电容器，电荷泵或电压调节器中的一个或多个。绝缘材料设置在电路上，并且通孔形成为穿过其中。金属带被设置成围绕子组件的外部连续，从而也形成与第二半导体电路的连接。电子组件金属带然后与半导体集成电路基板和封装的电路连接。

8. 发明授权

US6157236A Parametric tuning of an integrated circuit after fabrication 失效
公开(公告)号：US6157236A
公开(公告)日：2000-12-05
申请号：US927237
申请日：1997-09-11
申请人： Sathyanandan Rajivan , Raoul B. Salem
发明人： Sathyanandan Rajivan , Raoul B. Salem
IPC分类号： H03K19/0175 , G01R31/30 , G01R31/317 , H03K5/00 , H03K19/00 , H03K19/0185 , H03K19/0948 , H03K19/173 , H03H11/26
CPC分类号： G01R31/30 , H03K19/0005 , H03K19/0027 , H03K19/018585 , H03K19/1731 , G01R31/31702 , H03K2005/00071
摘要： The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller. In turn, the tuning controller generates corresponding tuning pattern signals enabling target circuit(s) to changeably tune the target parameter by selectively enabling different tunable portions of the target circuit. For example, by selecting the appropriate load resistance and/or capacitance of the tunable circuit, the rise/fall time of the target circuit is tuned for compatibility with respect to the other portions of the IC or system. The tunable circuit of the present invention advantageously lends itself to post-fabrication correction of design or fabrication problems, thereby increasing the potential yield rate. In addition, the tunable circuit can be tested under different operating conditions in a non-destructive manner without the need for another time-consuming and costly IC fabrication cycle. Other advantages include the ability to selectively operate target circuit(s) of the IC at a higher speed under ideal conditions and at a lower speed under hostile conditions.

9. 发明授权

US6018450A Output driver with overshoot and undershoot protection 失效
标题翻译：输出驱动器，具有过冲和欠冲击保护
公开(公告)号：US6018450A
公开(公告)日：2000-01-25
申请号：US197274
申请日：1998-11-20
申请人： Waseem Ahmad , Raoul B. Salem
发明人： Waseem Ahmad , Raoul B. Salem
IPC分类号： H02H9/04 , H03K19/003 , H02H3/20
CPC分类号： H02H9/046 , H03K19/00315
摘要： A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot protection mechanism senses an overshoot voltage at the output terminal of the output driving element, it raises the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, thereby preventing overstress or damage to the element. When the undershoot protection mechanism senses an undershoot voltage at the output terminal of the output driving element, it lowers the voltage at the control terminal of the output driving element. This serves to maintain the voltage between the output terminal and the control terminal of the output driving element within a safe range, which in turn prevents overstress and damage to the element. The output driving circuit also has a recovery circuit for accelerating the process of returning the output driving element to normal operation after the effects of overshoot and undershoot have ceased. This aids in accelerating the operation of the output driving circuit.
摘要翻译：具有输出驱动元件，过冲保护机构和下冲保护机构的输出驱动电路。当过冲保护机构感测输出驱动元件的输出端子处的过冲电压时，升高输出驱动元件的控制端子处的电压。这用于将输出驱动元件的输出端子和控制端子之间的电压保持在安全范围内，从而防止元件的过应力或损坏。当下冲保护机构感测输出驱动元件的输出端子的下冲电压时，降低输出驱动元件的控制端子处的电压。这用于将输出驱动元件的输出端子和控制端子之间的电压保持在安全范围内，这进而防止元件的过应力和损坏。输出驱动电路还具有恢复电路，用于在过冲和下冲的影响停止之后，加速将输出驱动元件返回到正常操作的处理。这有助于加速输出驱动电路的运行。

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