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    • 4. 发明授权
    • Server virtualization
    • 服务器虚拟化
    • US08856303B2
    • 2014-10-07
    • US13343262
    • 2012-01-04
    • Vishal Anand
    • Vishal Anand
    • G06F15/173
    • H04L41/147G06F11/3409G06F11/3442G06F2201/815H04L41/0806H04L41/22
    • A resource requirements method and system is provided. The method includes identifying dependencies and calculating a utilization value for a source server. The source server is mapped to an application and a source infrastructure is compared to a target infrastructure. Deficiencies and differences associated with the target infrastructure are determined and dependency requirements for fulfillment in the target infrastructure are generated. The utilization value is compared to a resource capability of the target server and resource requirements for fulfillment on the target server are generated.
    • 提供资源需求方法和系统。 该方法包括识别源服务器的依赖性和计算利用率值。 源服务器映射到应用程序,并将源基础架构与目标基础架构进行比较。 确定与目标基础架构相关的缺陷和差异,并生成目标基础设施中履行的依赖性要求。 将利用价值与目标服务器的资源能力进行比较,生成目标服务器上的履行资源需求。
    • 6. 发明授权
    • Centrally controlled interface scheme for promoting design reusable
circuit blocks
    • 用于促进设计可重用电路块的集中控制接口方案
    • US6052754A
    • 2000-04-18
    • US79989
    • 1998-05-14
    • Vishal Anand
    • Vishal Anand
    • G06F13/362G06F13/00
    • G06F13/362
    • A centrally controlled interface scheme for promoting design reusable circuit blocks. A system in accordance with the present invention enables existing circuit blocks of a computer system to be connected in a wide variety of shared bus standards while their internal circuitry remains unchanged. Specifically, within an embodiment of the present invention, the sharing of signals over a shared bus scheme is exclusively controlled by external bus control circuits which are controlled by an external control unit. As such, the circuit blocks are designed to operate as if they have dedicated (e.g., point-to-point) lines to the other circuit blocks with which they communicate. By implementing the circuit blocks and external control of the shared signals in this fashion, the bus interconnection scheme of the circuit blocks can be changed to fit desired performance levels or expected traffic levels, while the circuit blocks themselves remain unchanged. Consequently, little or no time is required redesigning existing circuit blocks when bus modifications are implemented within future computer systems which still utilize the existing circuit blocks. Instead, only modifications are required to the external circuitry which controls the shared signals of the circuit blocks, which is substantially easier than redesigning existing circuit blocks.
    • 用于促进设计可重用电路块的集中控制接口方案。 根据本发明的系统使计算机系统的现有电路块能够以各种各样的共享总线标准连接,同时其内部电路保持不变。 具体地说,在本发明的一个实施例中,通过共享总线方案共享信号由外部控制单元控制的外部总线控制电路来控制。 这样,电路块被设计成像对它们通信的其他电路块具有专用(例如,点到点)线一样操作。 通过以这种方式实现共享信号的电路块和外部控制,可以改变电路块的总线互连方案以适应期望的性能水平或预期的业务量,而电路块本身保持不变。 因此,在仍然利用现有电路块的未来的计算机系统中实现总线修改时,很少或根本没有时间重新设计现有的电路块。 相反,仅需要对控制电路块的共享信号的外部电路进行修改,这比重新设计现有的电路块要容易得多。
    • 7. 发明授权
    • Method and system for latching an address for accessing synchronous
random access memory using a single address status signal control line
    • 用于使用单个地址状态信号控制线锁存用于访问同步随机存取存储器的地址的方法和系统
    • US6044432A
    • 2000-03-28
    • US968555
    • 1997-11-12
    • Vishal Anand
    • Vishal Anand
    • G06F12/08G11C7/10G11C8/06G06F12/00G11C11/413
    • G11C7/1072G06F12/0802G11C8/06
    • A method and system for latching an address for accessing a synchronous static random access memory (SRAM). A first address status signal of the SRAM is driven active, triggering an SRAM to latch the address on an address bus coupled therewith. A second address status signal is received when a valid address is placed on the address bus. In response, the first address status signal is driven inactive. This forces the last address latched by the SRAM to be the one indicated by the second address status signal. Then, a determination is made as to whether SRAM access is required based on the address placed on the bus. SRAM access may not be required if the current cycle is either non-cacheable or a miss in the SRAM. When SRAM access is not required, the first address status signal is driven active. In the alternative, when SRAM access is required, the first address status signal is maintained inactive. The first address status signal is maintained inactive until the SRAM is ready to accept a second address.
    • 一种用于锁存用于访问同步静态随机存取存储器(SRAM)的地址的方法和系统。 SRAM的第一地址状态信号被驱动为有效,触发SRAM以与其耦合的地址总线上的地址锁存。 当有效地址被放置在地址总线上时,接收到第二个地址状态信号。 作为响应,第一地址状态信号被驱动为无效。 这迫使由SRAM锁存的最后一个地址是由第二个地址状态信号指示的地址。 然后,根据总线上的地址确定是否需要SRAM访问。 如果当前周期是不可缓存的或SRAM中的未命中,则可能不需要SRAM访问。 当不需要SRAM访问时,第一个地址状态信号被驱动为有效。 或者,当需要SRAM访问时,第一地址状态信号保持不活动。 第一个地址状态信号保持不活动,直到SRAM准备好接受第二个地址。
    • 10. 发明授权
    • High performance internal bus for promoting design reuse in north bridge chips
    • 高性能内部总线,用于促进北桥芯片的设计重用
    • US06581124B1
    • 2003-06-17
    • US09079498
    • 1998-05-14
    • Vishal Anand
    • Vishal Anand
    • G06F1314
    • H04L67/42G06F9/542H04L12/1895H04L29/06H04L67/14H04L69/08H04L69/16H04L69/161H04L69/165
    • In an example embodiment, an apparatus providing communication in a computer system, comprises, a plurality of modules each having a master port and a slave port A secondary bus is shared between the plurality of modules for transmitting data and address information between a master port and a slave port of two modules. A bridge circuit coupled to the plurality of modules and the secondary bus, individually grants modules of the plurality of modules, access to the secondary bus. The bridge circuit establishes point-to-point communication paths between a master port and a slave port of two modules of the plurality of modules, for communicating handshake signals between them, and controls address and data phases between modules; two address phases can be outstanding simultaneously. The bridge circuit forwards address and data phases from one module to another module of the plurality of modules; the plurality of modules only interface with the bridge circuit.
    • 在一个示例性实施例中,一种在计算机系统中提供通信的装置包括多个模块,每个模块具有主端口和从端口。在多个模块之间共享辅助总线,用于在主端口和主端口之间传输数据和地址信息 两个模块的从站端口。 耦合到所述多个模块和所述辅助总线的桥接电路单独地授予所述多个模块的模块,访问所述辅助总线。 桥电路在多个模块的两个模块的主端口和从端口之间建立点对点通信路径,用于在它们之间通信握手信号,并且控制模块之间的地址和数据相位; 两个地址阶段可以同时出色。 桥接电路将地址和数据相位从一个模块转移到多个模块的另一个模块; 多个模块仅与桥接电路接口。