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1. 发明授权

US08001497B2 Control signal source replication 有权
标题翻译：控制信号源复制
公开(公告)号：US08001497B2
公开(公告)日：2011-08-16
申请号：US12243768
申请日：2008-10-01
申请人： Randall P. Fry , Balamurugan Balasubramanian , Kavitha Chaturvedula
发明人： Randall P. Fry , Balamurugan Balasubramanian , Kavitha Chaturvedula
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/505 , G06F2217/84
摘要： Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.
摘要翻译：公开了一种复制控制信号源的方法，包括：接收功能块的描述，该功能块包括多个多路复用器结构，多个存储块和至少一个复用器结构的组合中的至少一个，并且至少一个记忆块识别控制所述多个多路复用器结构，所述多个存储器块中的至少一个以及至少一个复用器结构和至少一个存储器块的所述组合的控制信号; 并且，确定第一副本控制信号和第二复制控制信号，所述第一副本控制信号和所述第二副本控制信号共同起到所述控制信号的作用，以控制所述多个多路复用器结构中的至少一个，所述多个存储器块，以及所述至少一个复用器结构和至少一个存储器块的组合。

2. 发明申请

US20100083195A1 CONTROL SIGNAL SOURCE REPLICATION 有权
标题翻译：控制信号源的复制
公开(公告)号：US20100083195A1
公开(公告)日：2010-04-01
申请号：US12243768
申请日：2008-10-01
申请人： Randall P. Fry , Balamurugan Balasubramanian , Kavitha Chaturvedula
发明人： Randall P. Fry , Balamurugan Balasubramanian , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.
摘要翻译：公开了一种复制控制信号源的方法，包括：接收功能块的描述，该功能块包括多个多路复用器结构，多个存储块和至少一个复用器结构的组合中的至少一个，并且至少一个记忆块识别控制所述多个多路复用器结构，所述多个存储器块中的至少一个以及至少一个复用器结构和至少一个存储器块的所述组合的控制信号; 并且，确定第一副本控制信号和第二复制控制信号，所述第一副本控制信号和所述第二副本控制信号共同起到所述控制信号的作用，以控制所述多个多路复用器结构中的至少一个，所述多个存储器块，以及所述至少一个复用器结构和至少一个存储器块的组合。

3. 发明授权

US07082584B2 Automated analysis of RTL code containing ASIC vendor rules 有权
标题翻译：自动分析包含ASIC供应商规则的RTL代码
公开(公告)号：US07082584B2
公开(公告)日：2006-07-25
申请号：US10427609
申请日：2003-04-30
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
摘要翻译：一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。选择了一种集成电路设计供应商的设计规则的RTL平台。设计规则从图形用户界面的RTL平台显示。从图形用户界面中选择了多个设计规则。在RTL代码的RTL平台中对每个选定的设计规则进行分析。生成分析结果作为每个选定设计规则的输出。

4. 发明授权

US07415687B2 Method and computer program for incremental placement and routing with nested shells 失效
标题翻译：方法和计算机程序，用于带嵌套外壳的增量放置和路由
公开(公告)号：US07415687B2
公开(公告)日：2008-08-19
申请号：US11244530
申请日：2005-10-05
申请人： Juergen K. Lahner , Balamurugan Balasubramanian , Randall P. Fry
发明人： Juergen K. Lahner , Balamurugan Balasubramanian , Randall P. Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.
摘要翻译：放置和布线集成电路设计的方法包括为集成电路设计的至少一部分生成初始放置和布线。分析集成电路设计的初始放置和路由，以找到关键位置，并将其分成一系列嵌套的shell。每个外壳围绕关键位置和每个前面的外壳。为每个shell选择shell的排序和时序约束和面积约束中的至少一个。每个外壳按照时序约束和面积限制选择的顺序放置和布线。

5. 发明授权

US08166428B2 Synthesized logic replacement 失效
标题翻译：合成逻辑更换
公开(公告)号：US08166428B2
公开(公告)日：2012-04-24
申请号：US12193566
申请日：2008-08-18
申请人： Randall P. Fry
发明人： Randall P. Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer.
摘要翻译：公开了一种改进合成电路设计的方法，包括搜索合成电路设计用于第一门控模式的第一实例。第一个实例从合成电路设计中删除。第一个实例被替换为非合成单元。改变多路复用器实现的方法包括接收描述合成逻辑电路设计的网表。分析网表以检测实现第一多路复用器的门的第一模式的第一实例。网络表中的第一个实例被替换为第一个多路复用器的技术实现。

6. 发明授权

US07380228B2 Method of associating timing violations with critical structures in an integrated circuit design 失效
标题翻译：将定时违规与集成电路设计中的关键结构相关联的方法
公开(公告)号：US07380228B2
公开(公告)日：2008-05-27
申请号：US10984115
申请日：2004-11-08
申请人： Randall P. Fry , Gregory Pierce , Juergen Lahner
发明人： Randall P. Fry , Gregory Pierce , Juergen Lahner
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.
摘要翻译：一种用于将定时违规与关键结构相关联的集成电路设计的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的关键结构; 以及（c）生成用于静态时序分析工具的输出脚本，该工具包括对关键结构的输入端具有起始点的路径的定时检查以及临界结构输出端的终点。

7. 发明申请

US20100262941A1 Automated Timing Optimization 失效
标题翻译：自动定时优化
公开(公告)号：US20100262941A1
公开(公告)日：2010-10-14
申请号：US12421198
申请日：2009-04-09
申请人： Randall P. Fry , Michael A. MInter
发明人： Randall P. Fry , Michael A. MInter
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84
摘要： A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.
摘要翻译：一种用于通过利用处理器识别集成电路设计中的负松弛路径，然后通过确定在前面布置的路径的定时松弛来识别正的松弛路径来减小集成电路设计中的负松弛路径中的定时违规的方法并且在消极的松弛路径之后。通过在正的松弛路径上执行额外的时序优化来确定是否可以从正的松弛路径获得裕度，并且确定该余量是否足以将定时违反减少到至少期望的水平。如果余量足够，则在正的松弛路径上执行附加的时序优化，并且使用余量来操纵时钟偏移并减少负的松弛路径上的定时违反。

8. 发明授权

US08336012B2 Automated timing optimization 失效
标题翻译：自动定时优化
公开(公告)号：US08336012B2
公开(公告)日：2012-12-18
申请号：US12421198
申请日：2009-04-09
申请人： Randall P. Fry , Michael A. MInter
发明人： Randall P. Fry , Michael A. MInter
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F2217/84
摘要： A method for reducing a timing violation in a negative slack path from an integrated circuit design, by identifying the negative slack path in the integrated circuit design with a processor, and then identifying positive slack paths by determining timing slack for the paths that are disposed before and after the negative slack path. A prediction is made as to whether margin can be obtained from the positive slack paths by performing additional timing optimization on the positive slack paths, and it is determined whether that margin is sufficient to reduce the timing violation to at least a desired level. If the margin is sufficient, then additional timing optimization is performed on the positive slack paths, and the margin is used to manipulate the clock skew and reduce the timing violation on the negative slack path.
摘要翻译：一种用于通过利用处理器识别集成电路设计中的负松弛路径，然后通过确定在前面布置的路径的定时松弛来识别正的松弛路径来减小集成电路设计中的负松弛路径中的定时违规的方法并且在消极的松弛路径之后。通过在正的松弛路径上执行额外的时序优化来确定是否可以从正的松弛路径获得裕度，并且确定该余量是否足以将定时违反减少到至少期望的水平。如果余量足够，则在正的松弛路径上执行附加的时序优化，并且使用余量来操纵时钟偏移并减少负的松弛路径上的定时违反。

9. 发明申请

US20100042966A1 MULTIPLEXER IMPLEMENTATION 失效
标题翻译：多路复用器实现
公开(公告)号：US20100042966A1
公开(公告)日：2010-02-18
申请号：US12193566
申请日：2008-08-18
申请人： Randall P. Fry
发明人： Randall P. Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer.
摘要翻译：公开了一种改进合成电路设计的方法，包括搜索合成电路设计用于第一门控模式的第一实例。第一个实例从合成电路设计中删除。第一个实例被替换为非合成单元。改变多路复用器实现的方法包括接收描述合成逻辑电路设计的网表。分析网表以检测实现第一多路复用器的门的第一模式的第一实例。网络表中的第一个实例被替换为第一个多路复用器的技术实现。

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