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1. 发明授权

US07082584B2 Automated analysis of RTL code containing ASIC vendor rules 有权
标题翻译：自动分析包含ASIC供应商规则的RTL代码
公开(公告)号：US07082584B2
公开(公告)日：2006-07-25
申请号：US10427609
申请日：2003-04-30
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
摘要翻译：一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。选择了一种集成电路设计供应商的设计规则的RTL平台。设计规则从图形用户界面的RTL平台显示。从图形用户界面中选择了多个设计规则。在RTL代码的RTL平台中对每个选定的设计规则进行分析。生成分析结果作为每个选定设计规则的输出。

2. 发明申请

US20050257180A1 Method of optimizing RTL code for multiplex structures 失效
标题翻译：优化多路复用结构的RTL码的方法
公开(公告)号：US20050257180A1
公开(公告)日：2005-11-17
申请号：US10844664
申请日：2004-05-12
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括以下步骤：（a）作为输入接收用于集成电路设计的第一寄存器传送级代码; （b）接收用户定义的最佳多路复用结构作为输入; （c）分析第一寄存器传送级代码以识别关键的多路复用结构; （d）将全局多路复用结构划分为与用户定义的最佳多路复用结构相同的本地多路复用结构; 以及（e）为所述集成电路设计产生用本地多路复用结构代替所述全局多路复用结构的第二寄存器传送级代码作为输出。

3. 发明申请

US20070079266A1 Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database 审中-公开
标题翻译：用于分析集成电路设计的方法和计算机程序，以使用设计闭包知识库和物理设计数据库来识别和解决以多规则违规为特征的有问题的结构
公开(公告)号：US20070079266A1
公开(公告)日：2007-04-05
申请号：US11241033
申请日：2005-09-30
申请人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
发明人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.
摘要翻译：一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的集成电路设计中的每个设计规则违规的主要和次要对象列表。每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略违反设计关闭指引报告。

4. 发明授权

US06438730B1 RTL code optimization for resource sharing structures 有权
标题翻译：用于资源共享结构的RTL代码优化
公开(公告)号：US06438730B1
公开(公告)日：2002-08-20
申请号：US09866661
申请日：2001-05-30
申请人： Kiran Atmakuri , Juergen Lahner , Gopinath Kudva
发明人： Kiran Atmakuri , Juergen Lahner , Gopinath Kudva
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system and method of optimizing a circuit design. The design may be coded in register transfer language (RTL) code. First the design code representing an integrated circuit design to be optimized is retrieved and sequentially searched for decision constructs. As each decision construct is encountered, it is checked to determine whether both branches drive a common output in response to a common select signal. If so, a determination is made whether the decision construct includes a common arithmetic operation in said both branches, and so, may be optimized. A construct library for a corresponding optimized construct and the selected decision construct is replaced with an optimized construct. After all of the decision constructs are checked, the optimized design code is stored, replacing the original design code. The optimized RTL design code has an identical logic function to the original retrieved RTL code.
摘要翻译：一种优化电路设计的系统和方法。该设计可以用寄存器传输语言（RTL）代码编码。首先，代表要优化的集成电路设计的设计代码被检索并依次搜索决策结构。当遇到每个决策构造时，检查确定两个分支是否响应于公共选择信号驱动公共输出。如果是这样，则确定决策构造是否包括在所述两个分支中的公共算术运算，因此可以被优化。用于相应的优化构造的构造库和所选择的决策构造被替换为优化的构造。检查所有决策结构后，存储优化的设计代码，替换原始设计代码。优化的RTL设计代码与原始检索的RTL代码具有相同的逻辑功能。

5. 发明授权

US07594201B2 Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code 失效
标题翻译：在RTL代码中优化多路复用结构和多路复用控制结构的增强方法
公开(公告)号：US07594201B2
公开(公告)日：2009-09-22
申请号：US11460680
申请日：2006-07-28
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F17/5077
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括用于集成电路设计的优化寄存器传送级代码的方法的步骤，包括以下步骤：接收用于集成电路设计的第一寄存器传送级代码和接收作为定义关键多路复用结构的输入标准。分析第一个寄存器传送电平代码以识别第一个寄存器传输电平代码中的多路复用结构。将在第一寄存器传送级代码中识别的多路复用结构中的每一个与定义关键复用结构的标准进行比较。在第一寄存器传送级代码中识别的满足定义关键复用结构的标准的多路复用结构中的每一个被输入到关键多路复用结构的列表中。关键复用结构列表作为输出生成。

6. 发明申请

US20060282801A1 ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CONTROL STRUCTURES IN RTL CODE 失效
标题翻译：在RTL代码中优化多重结构和多重控制结构的增强方法
公开(公告)号：US20060282801A1
公开(公告)日：2006-12-14
申请号：US11460680
申请日：2006-07-28
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F17/5077
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括用于集成电路设计的优化寄存器传输级代码的方法的步骤，包括以下步骤：接收用于集成电路设计的第一寄存器传送级代码和接收作为定义关键多路复用结构的输入标准。分析第一个寄存器传送电平代码以识别第一个寄存器传输电平代码中的多路复用结构。将在第一寄存器传送级代码中识别的多路复用结构中的每一个与定义关键复用结构的标准进行比较。在第一寄存器传送级代码中识别的满足定义关键复用结构的标准的多路复用结构中的每一个被输入到关键多路复用结构的列表中。关键复用结构列表作为输出生成。

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