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1. 发明申请

US20060268179A1 Motion detector for a video display system 有权
标题翻译：用于视频显示系统的运动检测器
公开(公告)号：US20060268179A1
公开(公告)日：2006-11-30
申请号：US11135799
申请日：2005-05-24
申请人： Karl Renner , Weider Chang , Ramesh Chandrasekaran
发明人： Karl Renner , Weider Chang , Ramesh Chandrasekaran
IPC分类号： H04N9/78
CPC分类号： H04N11/146 , H04N5/145 , H04N9/66 , H04N9/77 , H04N9/78 , H04N11/165
摘要： Systems and methods are provided for detecting motion within a composite video signal. A first chroma difference element compares an in-phase chroma component of the composite video signal to a delayed representation of the in-phase chroma component to produce a first chroma difference value for a given pixel. A second chroma difference element compares a quadrature chroma component of the composite video signal to a delayed representation of the quadrature chroma component to produce a second chroma difference value for the pixel. A parameter mapping component maps the first and second difference values to respective first and second motion parameters that indicates the degree of change in the chroma properties of the pixel. A parameter selector determines a composite motion parameter for the pixel from the first and second motion parameters.
摘要翻译：提供用于检测复合视频信号内的运动的系统和方法。第一色差元件将复合视频信号的同相色度分量与同相色度分量的延迟表示进行比较，以产生给定像素的第一色度差值。第二色差元件将复合视频信号的正交色度分量与正交色度分量的延迟表示进行比较，以产生像素的第二色度差值。参数映射组件将第一和第二差分值映射到指示像素的色度特性的变化程度的相应的第一和第二运动参数。参数选择器从第一和第二运动参数确定像素的复合运动参数。

2. 发明申请

US20060268178A1 Systems and methods for separating luma and chroma information in a composite video signal 有权
标题翻译：用于在复合视频信号中分离亮度和色度信息的系统和方法
公开(公告)号：US20060268178A1
公开(公告)日：2006-11-30
申请号：US11135758
申请日：2005-05-24
申请人： Weider Chang , Karl Renner , Ramesh Chandrasekaran , Steven Clynes , Jason Meiners
发明人： Weider Chang , Karl Renner , Ramesh Chandrasekaran , Steven Clynes , Jason Meiners
IPC分类号： H04N9/78
CPC分类号： H04N9/78
摘要： Systems and method are provided for luma-chroma separation. A demodulator system demodulates a composite video signal to produce at least two baseband chroma signals. A given baseband chroma signal contains chroma information for one of a plurality of video frames comprising the composite signal. A three-dimensional (3-D) comb filter removes luma information from a given baseband chroma signal by combining sets of at least two baseband chroma signals to form a 3-D filtered baseband signal.
摘要翻译：提供了用于亮度色度分离的系统和方法。解调器系统解调复合视频信号以产生至少两个基带色度信号。给定的基带色度信号包含包含复合信号的多个视频帧之一的色度信息。三维（3-D）梳状滤波器通过组合至少两个基带色度信号的组合来从给定的基带色度信号中去除亮度信息，以形成3-D滤波的基带信号。

3. 发明申请

US20070076128A1 Method for treating inter-frame motion in a composite video signal 有权
标题翻译：在复合视频信号中处理帧间运动的方法
公开(公告)号：US20070076128A1
公开(公告)日：2007-04-05
申请号：US11240718
申请日：2005-10-01
申请人： Ramesh Chandrasekaran , Weider Chang , Karl Renner
发明人： Ramesh Chandrasekaran , Weider Chang , Karl Renner
IPC分类号： H04N5/14
CPC分类号： H04N5/144
摘要： A method for treating inter-frame motion in a series of consecutive signal frames of a composite video signal includes the steps of, for an evaluation pixel position in each frame of a test frame-set including three successive signal frames: (a) determining whether there is at least a predetermined difference in chroma component or in luma component signals at the evaluation pixel; (b) if in step (a) there is not a predetermined difference in chroma component signals or in luma component signals, determining whether a first and third frame of the test frame-set are substantially identical; (c) determining whether at least a first predetermined number of the luma or chroma component signals in the test frame-set present at least one false color; and (d) determining whether at least a second predetermined number of high frequency luma component signals exist in the test frame-set.
摘要翻译：一种用于处理复合视频信号的一系列连续信号帧中的帧间运动的方法包括以下步骤：对于包括三个连续信号帧的测试帧集合的每个帧中的评估像素位置：（a）确定是否评估像素处的色度分量或亮度分量信号中至少存在预定的差异; （b）如果在步骤（a）中色度分量信号或亮度分量信号中没有预定的差异，则确定测试帧组的第一和第三帧是否基本相同; （c）确定测试帧组中至少第一预定数量的亮度或色度分量信号是否存在至少一种假色; 和（d）确定在测试帧组中是否存在至少第二预定数量的高频亮度分量信号。

4. 发明申请

US20070064151A1 System and implementation for IF compensation for video decoders 有权
标题翻译：视频解码器IF补偿的系统和实现
公开(公告)号：US20070064151A1
公开(公告)日：2007-03-22
申请号：US11220488
申请日：2005-09-07
申请人： Weider Chang , Karl Renner , Shereef Shehata
发明人： Weider Chang , Karl Renner , Shereef Shehata
IPC分类号： H04N7/04
CPC分类号： H04N5/455 , H04B1/1027 , H04B1/123 , H04B10/85 , H04N9/646 , H04N21/4382 , H04N21/6118
摘要： Base band compensation for an IF stage in a television provides significant advantages over compensation applied to the composite signal. Each base band color difference signal is filtered to obtain cross-talk elements, which are then applied to the opposite channel to eliminate the cross-talk components from the color difference signal channels. The compensation technique is applicable to IF stages generally, including those based on SAW filters. High and low gain compensation of the cross-talk compensated signals may also be performed to reduce distortion in the compensated signals. The base band compensation tends to reduce or eliminate visual artifacts in a television image, especially where sharp contrast transitions occur in the image.
摘要翻译：电视中的IF级的基带补偿相对于复合信号的补偿提供了显着的优点。对每个基带色差信号进行滤波以获得串扰元件，然后将它们应用于相反通道，以消除色差信号通道中的串扰分量。补偿技术一般适用于IF级，包括基于SAW滤波器的IF级。也可以执行串扰补偿信号的高和低增益补偿以减少补偿信号中的失真。基带补偿趋向于减少或消除电视图像中的视觉伪影，特别是在图像中发生尖锐的对比度转换时。

5. 发明申请

US20070035667A1 Method and apparatus for digital MTS receiver 有权
标题翻译：数字MTS接收机的方法和装置
公开(公告)号：US20070035667A1
公开(公告)日：2007-02-15
申请号：US11199661
申请日：2005-08-09
申请人： Feng Ying , Karl Renner , Weider Chang , Shereef Shehata , Viet Dinh , Xiaodong Wu , Walter Demmer
发明人： Feng Ying , Karl Renner , Weider Chang , Shereef Shehata , Viet Dinh , Xiaodong Wu , Walter Demmer
IPC分类号： H04H5/00 , H04N7/00
CPC分类号： H04H40/45
摘要： System and method for an all-digital audio receiver for a BTSC MTS audio signal or other composite signal that is FM modulated. A preferred embodiment comprises a digital FM demodulator for receiving an analog to digital quantized SIF signal and performing demodulation and outputting a composite audio signal, and a digital audio processor for decomposing the composite audio signal into at least the SAP, stereo and monaural signals for audio reproduction. In a preferred embodiment, the digital audio processor is a programmable digital signal processor. In a preferred embodiment, the digital FM demodulator and the digital audio processor are implemented as an integrated circuit. Methods for processing the audio signal using the digital processors of the invention are provided.
摘要翻译：用于BTSC MTS音频信号或FM调制的其他复合信号的全数字音频接收机的系统和方法。优选实施例包括用于接收模数数字量化SIF信号并执行解调和输出复合音频信号的数字FM解调器，以及用于将复合音频信号分解为至少SAP，用于音频的立体声和单声道信号的数字音频处理器再生产。在优选实施例中，数字音频处理器是可编程数字信号处理器。在优选实施例中，数字FM解调器和数字音频处理器被实现为集成电路。提供了使用本发明的数字处理器来处理音频信号的方法。

6. 发明申请

US20060232709A1 Interframe noise reduction for video 有权
公开(公告)号：US20060232709A1
公开(公告)日：2006-10-19
申请号：US11109290
申请日：2005-04-19
申请人： Karl Renner , Shereef Shehata , Jason Meiners , Weider Chang
发明人： Karl Renner , Shereef Shehata , Jason Meiners , Weider Chang
IPC分类号： H04N5/00 , H04N9/78
CPC分类号： H04N9/646 , H04N5/21 , H04N5/911
摘要： A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.

7. 发明授权

US07173668B2 Equilibrium based horizontal sync detector for video decoder 有权
标题翻译：用于视频解码器的基于平衡的水平同步检测器
公开(公告)号：US07173668B2
公开(公告)日：2007-02-06
申请号：US10623232
申请日：2003-07-18
申请人： Karl Renner , Walter Heinrich Demmer , Jason M. Meiners , Weider Peter Chang , Airong Amy Zhang
发明人： Karl Renner , Walter Heinrich Demmer , Jason M. Meiners , Weider Peter Chang , Airong Amy Zhang
IPC分类号： H04N5/10 , H03L7/00
CPC分类号： H04N5/10
摘要： The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).
摘要翻译：本发明公开了一种包括滤波器部分（12），耦合到滤波器部分（12）的平衡累加器部分（14）的水平同步检测器电路（10），耦合到滤波器部分的水平同步检测器部分 12）和平衡累加器部分（14）以及耦合到水平同步检测器部分（16）的输出逻辑部分（18），输出逻辑部分（18）适于产生基于粗相位误差（108）和精细相位误差（112）的组合。

8. 发明申请

US20050018080A1 Equilibrium based horizontal sync detector for video decoder 有权
标题翻译：用于视频解码器的基于平衡的水平同步检测器
公开(公告)号：US20050018080A1
公开(公告)日：2005-01-27
申请号：US10623232
申请日：2003-07-18
申请人： Karl Renner , Walter Demmer , Jason Meiners
发明人： Karl Renner , Walter Demmer , Jason Meiners
IPC分类号： H04N5/10 , H03L7/00
CPC分类号： H04N5/10
摘要： The present invention discloses a horizontal sync detector circuit (10) comprising a filter portion (12), an equilibrium accumulator portion (14) coupled to the filter portion (12), a horizontal sync detector portion (16) coupled to the filter portion (12) and to the equilibrium accumulator portion (14), and an output logic portion (18) coupled to the horizontal sync detector portion (16), the output logic portion (18) adapted to produce a phase error (116) based on a combination of a coarse phase error (108) and a fine phase error (112).
摘要翻译：本发明公开了一种包括滤波器部分（12），耦合到滤波器部分（12）的平衡累加器部分（14）的水平同步检测器电路（10），耦合到滤波器部分的水平同步检测器部分 12）和平衡累加器部分（14）以及耦合到水平同步检测器部分（16）的输出逻辑部分（18），输出逻辑部分（18）适于产生基于粗相位误差（108）和精细相位误差（112）的组合。

9. 发明授权

US5036453A Master/slave sequencing processor 失效
标题翻译：主/从排序处理器
公开(公告)号：US5036453A
公开(公告)日：1991-07-30
申请号：US390507
申请日：1989-08-02
申请人： Karl Renner , John P. Shanklin
发明人： Karl Renner , John P. Shanklin
IPC分类号： G06F15/80
CPC分类号： G06F15/8015
摘要： An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.
摘要翻译：阵列处理器包括主阵列控制器和定序器（12）和多个从属处理器（20a） - （20n）。主机产生用于对每个从属处理器中的指令流进行排序的排序命令。从处理器产生相关存储器（34a） - （34n）的地址。存储器的数据输出通过交叉点开关（22）连接到从属数据处理器（24）。主机（12）可操作以将所有从机设备初始化为内部程序的起始地址，并以同步和并行方式对其中的指令流进行排序，以执行特定任务。

10. 发明申请

US20110131439A1 Jitter Precorrection Filter in Time-Average-Frequency Clocked Systems 有权
标题翻译：时间平均频率时钟系统中的抖动预校正滤波器
公开(公告)号：US20110131439A1
公开(公告)日：2011-06-02
申请号：US12628339
申请日：2009-12-01
申请人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
发明人： Karl Renner , Walter Heinrich Demmer , Liming Xiu
IPC分类号： H03L7/06 , H03M1/82 , H03L7/00 , G06F1/08
CPC分类号： G06F1/08 , H03L7/18
摘要： Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis circuitry generates internal clock signals of a desired frequency, for example as based on a recovered clock signal from an input data stream, in a manner in which not all periods of the clock signal are of uniform duration. A jitter precorrection filter is inserted into the data path to apply a variable delay to pre-correct for distortion caused by jitter in the clock cycle. In embodiments of the invention using a flying-adder architecture to generate the clock signal, coefficients of the digital filer realizing the jitter precorrection filter are calculated according to the currently-selected oscillator phase and according to a fractional portion of a digital frequency control word.
摘要翻译：用于处理数字数据的同步电路，其中数据被滤波以补偿时间平均频率时钟信号中的预期抖动。时间平均频率合成电路以不是所有的时钟信号周期具有均匀持续时间的方式，例如基于来自输入数据流的恢复的时钟信号来产生期望频率的内部时钟信号。抖动预校正滤波器被插入到数据路径中以应用可变延迟来预校正由时钟周期中的抖动引起的失真。在使用飞加法器架构来生成时钟信号的本发明的实施例中，根据当前选择的振荡器相位并根据数字频率控制字的小数部分来计算实现抖动预校正滤波器的数字滤波器的系数。

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