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1. 发明申请

US20160027515A1 Pulse Control For Non-Volatile Memory 有权
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：US20160027515A1
公开(公告)日：2016-01-28
申请号：US14878902
申请日：2015-10-08
申请人： Rambus Inc.
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C16/10 , G11C16/34 , G11C16/26 , G11C16/04
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

2. 发明授权

US09158672B1 Dynamic deterministic address translation for shuffled memory spaces 有权
标题翻译：混洗存储空间的动态确定性地址转换
公开(公告)号：US09158672B1
公开(公告)日：2015-10-13
申请号：US13644550
申请日：2012-10-04
申请人： Rambus Inc.
发明人： Hongzhong Zheng , Brent Steven Haukness
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/023 , G06F12/0238 , G06F2212/1024 , G06F2212/2022 , G06F2212/7201 , G06F2212/7211
摘要： A memory storage scheme specially adapted for wear leveling (or other reorganization of logical memory space). Memory space includes a logical memory space of M addressable blocks of data, stored as rows or pages, and N substitute rows or pages. Data is periodically shuffled by copying data from one of the M addressable blocks to a substitute row, with the donating row then becoming part of substitute memory space, available for ensuing wear leveling operations, using a stride address. The disclosed techniques enable equation-based address translation, obviating need for an address translation table. An embodiment performs address translation entirely in hardware, for example, integrated with a memory device to perform wear leveling or data scrambling, in a manner entirely transparent to a memory controller. In addition, the stride address can represent an offset greater than one (e.g., greater than one row) and can be dynamically varied.
摘要翻译：专门用于磨损均衡（或逻辑内存空间的其他重组）的存储器存储方案。存储器空间包括存储为行或页面的M个可寻址数据块的逻辑存储空间，以及N个替代行或页面。通过将数据从M个可寻址块中的一个复制到替代行来周期性地进行数据洗牌，然后捐赠行成为替代存储器空间的一部分，可用于随后进行的磨损均衡操作，使用跨步地址。所公开的技术使得基于方程式的地址转换不需要地址转换表。一个实施例，以对于存储器控制器完全透明的方式，完全在硬件上执行地址转换，例如与存储器件集成以执行损耗均衡或数据加扰。此外，步幅地址可以表示大于1的偏移（例如，大于一行），并且可以动态地变化。

3. 发明授权

US09087572B2 Content addressable memory 有权
标题翻译：内容可寻址内存
公开(公告)号：US09087572B2
公开(公告)日：2015-07-21
申请号：US14091213
申请日：2013-11-26
申请人： Rambus Inc.
发明人： Deepak Chandra Sekar , Brent Steven Haukness , John Eric Linstadt , Scott C. Best
IPC分类号： G11C7/00 , G11C15/00 , G11C13/00 , G11C15/04
CPC分类号： G11C15/00 , G11C13/0002 , G11C15/046
摘要： A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.
摘要翻译：内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。

4. 发明授权

US09564225B2 Pulse control for non-volatile memory 有权
标题翻译：用于非易失性存储器的脉冲控制
公开(公告)号：US09564225B2
公开(公告)日：2017-02-07
申请号：US14878902
申请日：2015-10-08
申请人： Rambus Inc.
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C16/10 , G11C16/12 , G11C16/34 , G11C16/04 , G11C16/26
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

5. 发明授权

US09111612B2 Direct relative measurement of memory durability 有权
标题翻译：直接相对测量记忆耐用性
公开(公告)号：US09111612B2
公开(公告)日：2015-08-18
申请号：US13788233
申请日：2013-03-07
申请人： RAMBUS INC.
发明人： Eric Linstadt , Brent Steven Haukness , J. James Tringali
IPC分类号： G06F7/02 , G01R31/28 , G11C13/00 , G11C29/38 , G11C29/50
CPC分类号： G11C13/0035 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C14/00 , G11C29/38 , G11C29/50008 , G11C2013/0054 , G11C2029/5002 , G11C2213/79
摘要： Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
摘要翻译：公开了包括多个电阻变化存储单元的存储器，其包括至少第一组和第二组存储单元，以及比较电路，被配置为进行与第一组存储单元的剩余耐久性的直接相对比较第二组记忆单元的剩余耐力。

6. 发明申请

US20140247656A1 Pulse Control For NonVolatile Memory 有权
标题翻译：非易失性存储器的脉冲控制
公开(公告)号：US20140247656A1
公开(公告)日：2014-09-04
申请号：US14145962
申请日：2014-01-01
申请人： Rambus Inc.
发明人： Mark D. Kellam , Brent Steven Haukness , Gary B. Bronner , Kevin Donnelly
IPC分类号： G11C16/12 , G11C16/34
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/12 , G11C16/26 , G11C16/3459
摘要： A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.
摘要翻译：非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

7. 发明申请

US20140115296A1 Remapping Memory Cells Based on Future Endurance Measurements 有权
标题翻译：基于未来耐久性测量重新映射记忆单元
公开(公告)号：US20140115296A1
公开(公告)日：2014-04-24
申请号：US14058081
申请日：2013-10-18
申请人： Rambus Inc.
发明人： Trung Diep , John Eric Linstadt , J. James Tringali , Hongzhong Zheng , Brent Steven Haukness
IPC分类号： G06F12/10
CPC分类号： G06F12/0238 , G06F2212/7204 , G06F2212/7211 , G11C13/0028 , G11C13/0035 , G11C13/0069 , G11C29/50008 , G11C2029/0409 , G11C2213/72 , G11C2213/79
摘要： A method of operating a memory device that includes groups of memory cells is presented. The groups include a first group of memory cells. Each one of the groups has a respective physical address and is initially associated with a respective logical address. The device also includes an additional group of memory cells that has a physical address but is not initially associated with a logical address. In the method, a difference in the future endurance between the first group of memory cells and the additional group of memory cells is identified. When the difference in the future endurance between the first group and the additional group exceeds a predetermined threshold difference, the association between the first group and the logical address initially associated with the first group is ended and the additional group is associated with the logical address that was initially associated with the first group.
摘要翻译：提出了一种操作包括存储器单元组的存储器件的方法。这些组包括第一组记忆单元。组中的每一个具有相应的物理地址，并且最初与相应的逻辑地址相关联。该设备还包括具有物理地址但不是最初与逻辑地址相关联的附加组的存储器单元。在该方法中，识别第一组存储器单元和附加的存储单元组之间的未来耐久性的差异。当第一组和附加组之间的未来耐久性的差异超过预定阈值差时，第一组与最初与第一组相关联的逻辑地址之间的关联结束，并且附加组与逻辑地址相关联，最初与第一组有关。

8. 发明申请

US20130235649A1 DIRECT RELATIVE MEASUREMENT OF MEMORY DURABILITY 审中-公开
标题翻译：直接相关测量记忆耐久性
公开(公告)号：US20130235649A1
公开(公告)日：2013-09-12
申请号：US13788233
申请日：2013-03-07
申请人： RAMBUS INC.
发明人： Eric Lindstadt , Brent Steven Haukness , J. James Tringali
IPC分类号： G11C13/00 , G11C29/38
CPC分类号： G11C13/0035 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C14/00 , G11C29/38 , G11C29/50008 , G11C2013/0054 , G11C2029/5002 , G11C2213/79
摘要： Disclosed is a memory including a plurality of resistive change memory cells, including at least a first group and a second group of the memory cells and a comparison circuit configured to conduct a direct relative comparison of a remaining endurance of the first group of memory cells to a remaining endurance of the second group of memory cells.
摘要翻译：公开了包括多个电阻变化存储单元的存储器，其包括至少第一组和第二组存储单元，以及比较电路，被配置为进行与第一组存储单元的剩余耐久性的直接相对比较第二组记忆单元的剩余耐力。

9. 发明申请

US20220334738A1 MEMORY MODULE WITH PERSISTENT CALIBRATION 有权
公开(公告)号：US20220334738A1
公开(公告)日：2022-10-20
申请号：US17721176
申请日：2022-04-14
申请人： Rambus Inc.
发明人： Thomas Vogelsang , Brent Steven Haukness
IPC分类号： G06F3/06
摘要： A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.

10. 发明申请

US20190164588A1 MEMORY COMPONENT WITH EFFICIENT WRITE OPERATIONS 审中-公开
公开(公告)号：US20190164588A1
公开(公告)日：2019-05-30
申请号：US16097579
申请日：2017-05-03
申请人： RAMBUS INC.
发明人： Frederick A. Ware , John Eric Linstadt , Brent Steven Haukness , Kenneth L. Wright , Thomas Vogelsang
IPC分类号： G11C11/403 , G11C11/406 , G11C11/409 , G11C11/408
摘要： A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.

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