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1. 发明授权

US5502315A Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
标题翻译：具有PECVD非晶硅元件的电可编程互连结构
公开(公告)号：US5502315A
公开(公告)日：1996-03-26
申请号：US161504
申请日：1993-12-02
申请人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
发明人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
IPC分类号： H01L23/525 , H02L27/02
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
摘要翻译：在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

2. 发明授权

US5989943A Method for fabrication of programmable interconnect structure 失效
公开(公告)号：US5989943A
公开(公告)日：1999-11-23
申请号：US447969
申请日：1989-12-08
申请人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
发明人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10 , H01L21/28
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

3. 发明授权

US6150199A Method for fabrication of programmable interconnect structure 有权
标题翻译：可编程互连结构的制造方法
公开(公告)号：US6150199A
公开(公告)日：2000-11-21
申请号：US405979
申请日：1999-09-27
申请人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
发明人： Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas , Hua-Thye Chua , Andrew K. Chan , John M. Birkner
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.
摘要翻译：在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

4. 发明授权

US5780919A Electrically programmable interconnect structure having a PECVD amorphous silicon element 失效
标题翻译：具有PECVD非晶硅元件的电可编程互连结构
公开(公告)号：US5780919A
公开(公告)日：1998-07-14
申请号：US646823
申请日：1996-05-21
申请人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
发明人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
IPC分类号： H01L21/82 , H01L23/525 , H01L27/10 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.
摘要翻译：在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。描述了用反熔丝形成现场可编程门阵列的方法。

5. 发明授权

US5717230A Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses 失效
标题翻译：现场可编程门阵列具有可再现的金属至金属非晶硅反熔丝
公开(公告)号：US5717230A
公开(公告)日：1998-02-10
申请号：US323168
申请日：1994-10-13
申请人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
发明人： Hua-Thye Chua , Andrew K. Chan , John M. Birkner , Ralph G. Whitten , Richard L. Bechtel , Mammen Thomas
IPC分类号： H01L23/525 , H01L27/02
CPC分类号： H01L23/5252 , H01L2924/0002
摘要： A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.
摘要翻译：现场可编程门阵列具有包括金属信号导体和金属对金属PECVD非晶硅反熔丝的可编程互连结构。金属对金属PECVD非晶硅反熔丝具有至少550兆欧姆的未编程电阻和低于200欧姆的编程电阻。

6. 发明授权

US09547968B2 Pre-smoke detector and system for use in early detection of developing fires 有权
标题翻译：用于早期发现火灾的烟雾探测器和系统
公开(公告)号：US09547968B2
公开(公告)日：2017-01-17
申请号：US13274765
申请日：2011-10-17
申请人： Jesse D. Adams , Ralph G. Whitten
发明人： Jesse D. Adams , Ralph G. Whitten
IPC分类号： G08B17/117 , G08B17/10 , G01N29/02 , G01N1/22
CPC分类号： G08B17/117 , G01N1/2214 , G01N5/02 , G01N25/00 , G01N25/4893 , G01N29/022 , G01N33/0047 , G01N2291/0256 , G08B17/10
摘要： A pre-smoke detector and system for use in early detection of developing fires whereby vapors of marker chemicals generated during the melting and/or smoldering of common household materials are detected before detection by conventional smoke detectors. Vapors resulting from heating and resultant vaporization of substances are detected as well as vapors resulting from their breakdown, decomposition, or pyrolysis during the pre-combustion stage. Conventional smoke detectors focus on particle detection and are most effective after a developing fire has produced smoke. To minimize false alarms caused by common household odors, the pre-smoke detectors focus on detecting medium temperature pyrolysis products using sensor coatings that can be consistent with a 10 year operational lifetime and multiple orthogonal detection processes. Since virtually all marker chemicals of interest for pre-smoke detection are heavier than air, a system is described that appropriately integrates with smoke detector alarm systems present in most homes.
摘要翻译：用于早期检测发展中火灾的烟雾前检测器和系统，其中在常规烟雾探测器检测之前检测到在普通家用材料的熔化和/或阴燃期间产生的标记化学品的蒸气。检测由物质的加热和所得蒸发产生的蒸气以及在预燃烧阶段由它们分解，分解或热解产生的蒸气。传统的烟雾探测器专注于颗粒检测，并且在发生火灾产生烟雾之后是最有效的。为了尽量减少普通家庭臭味引起的假警报，烟雾探测器集中在使用传感器涂层检测中温热解产物，这可以与10年的使用寿命和多个正交检测过程保持一致。由于几乎所有用于预烟雾检测的标记物质都比空气重，所以描述了适合与多数家庭中存在的烟雾探测器报警系统集成的系统。

7. 发明授权

US06940093B2 Special contact points for accessing internal circuitry of an integrated circuit 失效
标题翻译：用于访问集成电路内部电路的特殊接点
公开(公告)号：US06940093B2
公开(公告)日：2005-09-06
申请号：US09753309
申请日：2000-12-29
申请人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
发明人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
IPC分类号： G01R1/073 , H01L23/50 , H01L23/58 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
摘要翻译：本发明的一个实施例涉及包括接合焊盘和特殊接触焊盘或点的集成电路。接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。特别的接触垫可以有利地以高度的位置自由度位于集成电路上。对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。特殊接触点也可用于选择故障电路的冗余电路。

8. 发明授权

US06597187B2 Special contact points for accessing internal circuitry of an integrated circuit 失效
标题翻译：用于访问集成电路内部电路的特殊接点
公开(公告)号：US06597187B2
公开(公告)日：2003-07-22
申请号：US09752902
申请日：2000-12-29
申请人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
发明人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
IPC分类号： G01R3102
CPC分类号： G01R1/07307 , G01R31/2884 , G01R31/31723 , H01L22/32 , H01L23/50 , H01L23/60 , H01L2224/0401 , H01L2224/05554 , H01L2224/16 , H01L2924/00013 , H01L2924/01079 , H01L2924/10253 , H01L2224/29099 , H01L2924/00
摘要： An integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing the internal circuits. The special contact pads may be advantageously located on the integrated circuit with a high degree of positional freedom. For one embodiment, the special contact pads may be disposed on the die at a location that is not in the same alignment as the bond pads. The special contact pads may be smaller than the bond pads so as not to increase the die size due to the special contact pads. The special contact points may also be used to externally program internal circuits (e.g., nonvolatile circuits) at the die or package level. The special contact points may also be used to select redundant circuits for faulty circuits.
摘要翻译：一种集成电路，包括接合焊盘和特殊接触焊盘或点。接合焊盘用于将集成电路作为整体与外部电路接口，并且将被连接到封装或电路板。接合焊盘以预定的对准方式设置在管芯上，例如外围，栅格或中心对准。特殊接触焊盘用于向内部电路提供外部测试模式和/或外部监测测试内部电路的结果。特别的接触垫可以有利地以高度的位置自由度位于集成电路上。对于一个实施例，特殊接触焊盘可以在与焊盘不同于对准的位置处设置在管芯上。特殊的接触焊盘可以小于接合焊盘，以便不会由于特殊的接触垫而增加管芯的尺寸。特殊接触点也可以用于在芯片或封装级别外部编程内部电路（例如非易失性电路）。特殊接触点也可用于选择故障电路的冗余电路。

9. 发明授权

US06429029B1 Concurrent design and subsequent partitioning of product and test die 失效
标题翻译：产品和测试模具的并行设计和后续划分
公开(公告)号：US06429029B1
公开(公告)日：2002-08-06
申请号：US09224166
申请日：1998-12-31
申请人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
发明人： Benjamin N. Eldridge , Igor Y. Khandros , David V. Pedersen , Ralph G. Whitten
IPC分类号： H01L2166
CPC分类号： G01R31/2884 , G01R31/2886 , H01L23/49811 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K3/20 , H05K3/3421 , H01L2924/00014 , H01L2924/00
摘要： One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die.
摘要翻译：本发明的一个实施例涉及用于产生用于产品模具的测试模具的设计方法，包括在统一设计中同时设计测试电路和产品电路的步骤。测试电路可以设计成为相应的产品电路提供高度的故障覆盖，通常不考虑测试电路所需的硅面积的量。然后，设计方法将统一设计分为测试模具和产品模具。测试芯片包括测试电路，产品芯片包括产品电路。然后可以在单独的半导体晶片上制造产品和测试裸片。通过将产品电路和测试电路划分为单独的管芯，可以在产品管芯上消除或最小化嵌入式测试电路。这将倾向于减小产品模具的尺寸并降低制造产品模具的成本，同时保持产品模具内的产品电路的高度测试覆盖。

10. 发明授权

US4796075A Fusible link structure for integrated circuits 失效
标题翻译：用于集成电路的可熔链接结构
公开(公告)号：US4796075A
公开(公告)日：1989-01-03
申请号：US852473
申请日：1986-04-15
申请人： Ralph G. Whitten
发明人： Ralph G. Whitten
IPC分类号： H01L23/525 , H01L27/02 , H01L23/48 , H01L29/34
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： A fusible link structure and method of making the same for use in integrated circuit structures is provided in which the fusible link comprises, in one embodiment, an alloy of platinum and silicon. The preferred alloy comprises the eutectic mixture having approximately 23 atomic percent silicon. Electrical connections to the fusible link are preferably provided by a layer of aluminum on a layer of material, preferably an alloy of titanium and tungsten wherein the titanium and tungsten alloy is disposed between the fusible link and the aluminum layer, and serves as a diffusion barrier for preventing diffusion of the aluminum into the fusible link. In a preferred embodiment, a fusible link is deposited on a relatively thick dielectric layer, preferably more than 10,000 .ANG. thick, having a relatively low thermal conductivity. The preferred method of depositing the fusible link is sputtering from a target comprising the platinum-silicide alloy, thus achieving a fuse element having uniform composition throughout its cross section. A fuse of this type has high reliability, requires low fusing current, and is dielectrically encapsulated sealed within the integrated circuit structure.
摘要翻译：提供了一种用于集成电路结构的可熔链接结构及其制造方法，其中在一个实施例中，可熔连接件包括铂和硅的合金。优选的合金包括具有约23原子％硅的共晶混合物。与可熔连接件的电连接优选地通过一层铝材料提供，优选钛和钨的合金，其中钛和钨合金设置在可熔连接件和铝层之间，并且用作扩散阻挡层用于防止铝扩散到熔丝中。在优选实施例中，可熔连接层沉积在相对较厚的电介质层上，优选厚度大于10,000，具有较低的热导率。沉积可熔连接件的优选方法是从包括铂硅化物合金的靶溅射，从而实现了在其横截面上具有均匀组成的熔丝元件。这种类型的保险丝具有高可靠性，需要低熔断电流，并且被集成地封装在集成电路结构内。

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