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1. 发明授权

US5371422A Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements 失效
标题翻译：可编程逻辑器件具有随机连接到全局导体的多路复用器和解复用器，用于逻辑元件之间的互连
公开(公告)号：US5371422A
公开(公告)日：1994-12-06
申请号：US38787
申请日：1993-03-29
申请人： Rakesh H. Patel , John E. Turner , Myron W. Wong
发明人： Rakesh H. Patel , John E. Turner , Myron W. Wong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. The logic array blocks and the connections between conductors are configured using programmable multiplexers and demultiplexers. Redundant conductive pathways are provided so that the programmable logic device may be efficiently programmed to perform a variety of logic functions. Furthermore, logic is provided with each logic array block that allows the global horizontal and vertical conductors to be interconnected without directly involving the logic in the logic array block, which therefore can be used to provide greater logical functionality.
摘要翻译：提供了具有逻辑阵列块的二维阵列的可编程逻辑器件。包含高级宏单元的逻辑阵列块包含基于pterm逻辑的可编程输入阵列，并与全局水平和垂直导体二维互连。使用可编程多路复用器和解复用器配置逻辑阵列块和导体之间的连接。提供了冗余导电路径，使得可编程逻辑器件可被有效地编程以执行各种逻辑功能。此外，提供了每个逻辑阵列块的逻辑，其允许全局水平和垂直导体互连，而不直接涉及逻辑阵列块中的逻辑，因此逻辑阵列块可用于提供更大的逻辑功能。

2. 发明授权

US06252422B1 Overvoltage-tolerant interface for intergrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06252422B1
公开(公告)日：2001-06-26
申请号：US09400953
申请日：1999-09-22
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

3. 发明授权

US6122209A Method of margin testing programmable interconnect cell 失效
标题翻译：可靠性测试方法可编程互连单元
公开(公告)号：US6122209A
公开(公告)日：2000-09-19
申请号：US350084
申请日：1999-07-08
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
摘要翻译：用于在集成电路中实现可编程互连的静态，非易失性和可编程可编程互连结单元。可编程互连结（600）可编程地配置为耦合或去耦第一互连线（210）和第二互连线（220）。直接检测可编程互连结的配置状态，并且在正常操作期间不需要诸如读出放大器的存储单元检测电路。全轨电压可以从第一互连线和第二互连线传递。

4. 发明授权

US06604228B1 Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions 有权
标题翻译：制造具有与不同工作电压条件兼容的接口的集成电路的技术
公开(公告)号：US06604228B1
公开(公告)日：2003-08-05
申请号：US09699305
申请日：2000-10-26
申请人： Rakesh H. Patel , John E. Turner
发明人： Rakesh H. Patel , John E. Turner
IPC分类号： G06F1750
CPC分类号： H03K19/0027 , H03K19/00315 , H03K19/017581 , H03K19/018521 , H03K19/018585
摘要： A technique of fabricating an integrated circuit adaptable for use in various operating voltage environments. The same integrated circuit design may be used in different operating modes depending on the particular option selected. For example, there may be three options (710, 715, 720). The various options of the integrated circuit formed on the same integrated circuit. During the fabrication of the integrated circuit, the desired option is selected. This may be accomplished, for example, by selecting the appropriate metal masks (725). Other techniques include, to name a few, using programmable links, programmable fuses, programmable cells, and many others. The technique of the present invention reduces the costs of integrated circuits. The same design may be used for a variety of purposes and in a variety of voltage environments without needing to develop and design a specific integrated circuit for each voltage condition.
摘要翻译：制造适用于各种工作电压环境的集成电路的技术。根据所选择的特定选项，可以在不同的操作模式中使用相同的集成电路设计。例如，可能有三个选项（710,715,720）。在同一集成电路上形成的集成电路的各种选项。在制造集成电路期间，选择期望的选项。这可以例如通过选择适当的金属掩模（725）来实现。其他技术包括仅举几例，使用可编程链路，可编程保险丝，可编程单元等等。本发明的技术降低了集成电路的成本。相同的设计可以用于各种目的和各种电压环境中，而不需要为每个电压条件开发和设计特定的集成电路。

5. 发明授权

US06573138B1 Nonvolatile memory cell with low doping region 有权
公开(公告)号：US06573138B1
公开(公告)日：2003-06-03
申请号：US09349533
申请日：1999-07-08
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L21336
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

6. 发明授权

US06433585B1 Overvoltage-tolerant interface for integrated circuits 有权
标题翻译：集成电路的过压容限接口
公开(公告)号：US06433585B1
公开(公告)日：2002-08-13
申请号：US09401145
申请日：1999-09-22
申请人： Rakesh H. Patel , John E. Turner , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , Wilson Wong
IPC分类号： H03K19094
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： An input/output driver for interfacing directly with a voltage at a pad (820) which is above a supply voltage (817) for the input/output driver. This may be referred to as an “overvoltage condition.” For example, if the supply voltage is 3.3 volts, a 5-volt signal may be provided at the pad of the input/output driver. The input/output driver will tolerate this voltage level and prevent leakage current paths. This will improve the performance, reliability, and longevity of the integrated circuit. The input/output driver includes a well-bias generator (1002) for preventing leakage current paths.
摘要翻译：一种用于直接与在输入/输出驱动器的电源电压（817）之上的焊盘（820）处的电压直接接口的输入/输出驱动器。这可能被称为“过电压条件”。例如，如果电源电压为3.3V，则可以在输入/输出驱动器的焊盘处提供5V电压信号。输入/输出驱动器将容忍该电压电平并防止漏电流路径。这将提高集成电路的性能，可靠性和使用寿命。输入/输出驱动器包括用于防止泄漏电流路径的阱偏压发生器（1002）。

7. 发明授权

US6118302A Interface for low-voltage semiconductor devices 失效
标题翻译：低压半导体器件接口
公开(公告)号：US6118302A
公开(公告)日：2000-09-12
申请号：US863905
申请日：1997-05-27
申请人： John E. Turner , Rakesh H. Patel
发明人： John E. Turner , Rakesh H. Patel
IPC分类号： H01L27/04 , G11C5/14 , H01L21/822 , H03K19/00 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique and circuitry to interface an integrated circuit to other circuits in a mixed-voltage mode environment. The integrated circuit operates at an internal supply voltage level. Externally, the integrated circuit will interface with an external supply voltage level, above the internal supply voltage level. The output signals from the integrated circuit will be compatible with the external supply level. Specifically, a level shifter (1317) or similar conversion circuit is used to convert voltages compatible with the internal supply level to be compatible with the external supply level.
摘要翻译：将集成电路与混合电压模式环境中的其他电路连接的技术和电路。集成电路在内部电源电压下工作。在外部，集成电路将与外部电源电压接口，高于内部电源电压电平。集成电路的输出信号将与外部电源电平兼容。具体地说，电平移位器（1317）或类似的转换电路用于将与内部电源电平兼容的电压转换为与外部电源电平兼容。

8. 发明授权

US6107854A Variable speed path circuit and method 失效
标题翻译：变速路径电路及方法
公开(公告)号：US6107854A
公开(公告)日：2000-08-22
申请号：US62379
申请日：1998-04-17
申请人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
发明人： Wilson Wong , John E. Turner , Thomas H. White , Rakesh H Patel
IPC分类号： H03K5/00 , H03K19/003 , H03K19/017 , H03K19/0185 , H03H11/26
CPC分类号： H03K19/00384 , H03K19/01721 , H03K19/018585 , H03K2005/00078
摘要： A speed path circuit includes a reference circuit and adjustable drive components that can be turned on or off to vary the speed path in order to meet minimum delay specification for the circuit. In an embodiment, one or more differential amplifiers are used to detect the strength of example circuit elements and generate a reference signal. An optional embodiment includes a mechanism for disconnecting the reference circuit to avoid any DC current drain. The invention may be used in a wide range of integrated circuits and may also be used in a programmable logic device (PLD). Reference circuits may be disconnected from a power source by using programmable logic elements.
摘要翻译：速度路径电路包括参考电路和可调节的驱动部件，其可以被接通或关断以改变速度路径，以便满足电路的最小延迟规范。在一个实施例中，使用一个或多个差分放大器来检测示例电路元件的强度并产生参考信号。可选实施例包括用于断开参考电路以避免任何直流电流消耗的机构。本发明可以用于广泛的集成电路中，并且还可以用在可编程逻辑器件（PLD）中。参考电路可以通过使用可编程逻辑元件与电源断开连接。

9. 发明授权

US06828620B2 Nonvolatile memory cell with low doping region 失效
标题翻译：具有低掺杂区域的非易失性存储单元
公开(公告)号：US06828620B2
公开(公告)日：2004-12-07
申请号：US10436644
申请日：2003-05-12
申请人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
发明人： Christopher J. Pass , James D. Sansbury , Raminda U. Madurawe , John E. Turner , Rakesh H. Patel , Peter J. Wright
IPC分类号： H01L29788
CPC分类号： H03K19/1776 , H03K19/17704 , H03K19/17736 , H03K19/1778
摘要： A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.
摘要翻译：制造非易失性器件的技术包括形成低掺杂区域以有助于还原衬底热电子。非易失性器件可以是诸如闪存，EEPROM或EPROM存储器单元的浮动栅极器件。低掺杂区域的掺杂浓度低于衬底的掺杂浓度。通过减少衬底热电子，这提高了非易失性器件的可靠性和寿命。

10. 发明授权

US06724222B2 Programmable logic with lower internal voltage circuitry 失效
标题翻译：具有较低内部电压电路的可编程逻辑
公开(公告)号：US06724222B2
公开(公告)日：2004-04-20
申请号：US10366814
申请日：2003-02-13
申请人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
发明人： Rakesh H. Patel , John E. Turner , John D. Lam , Wilson Wong
IPC分类号： H03K19175
CPC分类号： H03K19/018585 , H03K19/0027 , H03K19/00315 , H03K19/018521
摘要： A technique and circuitry interfaces a programmable logic integrated circuit compatible with one voltage level to other integrated circuits compatible with a different voltage level. In particular, an on-chip voltage less than the external supply level of the programmable logic integrated circuit is provided to a core portion of a programmable logic integrated circuit by way of a conversion transistor. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. Externally, the programmable logic integrated circuit will interface with an external supply voltage level. The input and output signals to and from the programmable logic integrated circuit will be compatible with the external supply level.
摘要翻译：技术和电路将与一个电压电平兼容的可编程逻辑集成电路与不同电压电平兼容的其他集成电路接口。特别地，通过转换晶体管将可编程逻辑集成电路的小于外部电源电平的片上电压提供给可编程逻辑集成电路的核心部分。在一个实施例中，转换晶体管的布局（或物理结构）分布在芯部分周围。在外部，可编程逻辑集成电路将与外部电源电压接口。来自可编程逻辑集成电路的输入和输出信号将与外部电源电平兼容。

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