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1. 发明申请

US20090303812A1 PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路的可编程脉宽调制和延迟发生电路
公开(公告)号：US20090303812A1
公开(公告)日：2009-12-10
申请号：US12543256
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C7/00 , G11C8/10 , G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

2. 发明授权

US07973549B2 Method and apparatus for calibrating internal pulses in an integrated circuit 有权
标题翻译：用于校准集成电路中的内部脉冲的方法和装置
公开(公告)号：US07973549B2
公开(公告)日：2011-07-05
申请号：US11761610
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译：用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。延迟链被配置为从片上电路部件接收脉冲信号。采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

3. 发明授权

US07701801B2 Programmable pulsewidth and delay generating circuit for integrated circuits 失效
标题翻译：用于集成电路的可编程脉冲宽度和延迟发生电路
公开(公告)号：US07701801B2
公开(公告)日：2010-04-20
申请号：US11761655
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

4. 发明申请

US20090309622A1 METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于在集成电路中校准内部脉冲的方法和装置
公开(公告)号：US20090309622A1
公开(公告)日：2009-12-17
申请号：US12543215
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译：用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。延迟链被配置为从片上电路部件接收脉冲信号。采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

5. 发明授权

US07869302B2 Programmable pulsewidth and delay generating circuit for integrated circuits 有权
标题翻译：用于集成电路的可编程脉冲宽度和延迟发生电路
公开(公告)号：US07869302B2
公开(公告)日：2011-01-11
申请号：US12543256
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

6. 发明申请

US20080310246A1 PROGRAMMABLE PULSEWIDTH AND DELAY GENERATING CIRCUIT FOR INTEGRATED CIRCUITS 失效
标题翻译：集成电路的可编程脉宽调制和延迟发生电路
公开(公告)号：US20080310246A1
公开(公告)日：2008-12-18
申请号：US11761655
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G11C8/00 , H03K19/00 , H03K3/017
CPC分类号： G11C11/413 , G11C11/41 , G11C29/12015 , G11C29/50 , G11C29/50012 , G11C2029/1202 , G11C2029/1208 , H03K5/06 , H03K5/13 , H03K5/1565
摘要： A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.
摘要翻译：本地片上可编程脉冲宽度和延迟产生电路包括被配置为接收全局时钟信号并输出本地时钟信号的时钟产生电路。时钟产生电路包括脉冲整形部分，其根据后沿延迟和前沿延迟中的至少一个调整全局时钟信号的脉冲宽度。前沿延迟由前沿延迟电路产生，并且后沿延迟由后沿延迟电路产生，后沿延迟电路被配置为对脉冲的后沿施加延迟。后沿延迟电路包括具有可编程级的延迟元件的延迟链，每个级都使用从地址锁存器解码的控制位独立控制。

7. 发明申请

US20080309364A1 METHOD AND APPARATUS FOR CALIBRATING INTERNAL PULSES IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于在集成电路中校准内部脉冲的方法和装置
公开(公告)号：US20080309364A1
公开(公告)日：2008-12-18
申请号：US11761610
申请日：2007-06-12
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
摘要翻译：用于测量内部脉冲的方法和电路包括使能电路，其被配置为从片上内置测试器接收控制信号以使得能够测量内部电路。延迟链被配置为从片上电路部件接收脉冲信号。采样锁存器各自包括耦合在延迟链的相邻延迟元件之间并与时钟信号同步的数据输入，使得通过比较输出序列中的相邻数字值来指示脉冲信号中的转变。

8. 发明授权

US07944229B2 Method and apparatus for calibrating internal pulses in an integrated circuit 有权
公开(公告)号：US07944229B2
公开(公告)日：2011-05-17
申请号：US12543215
申请日：2009-08-18
申请人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
发明人： Rajiv V. Joshi , Robert L. Franch , Robert Maurice Houle , Kevin A. Batson
IPC分类号： G01R31/02
CPC分类号： G01R31/31725 , G01R31/31726
摘要： A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.

9. 发明授权

US08767501B2 Self-reconfigurable address decoder for associative index extended caches 有权
标题翻译：用于关联索引扩展缓存的自重配置地址解码器
公开(公告)号：US08767501B2
公开(公告)日：2014-07-01
申请号：US13550762
申请日：2012-07-17
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G11C8/10
CPC分类号： G06F12/0864 , G06F2212/1021 , G11C15/04
摘要： Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
摘要翻译：关联索引扩展（AIX）缓存可以通过采用可编程线解码的可重构解码器进行功能实现。可重配置解码器具有线路数量的可扩展性，索引扩展位的数量和存储体的数量。可重构解码器可以在纯直接映射（DM）模式和直接映射关联索引扩展（DM-AIX）操作模式之间切换。对于组合配置，可重构解码器能够以DM模式运行某些存储区，并以DM-AIX模式运行其他存储区。采用该可重构解码器的高速缓存器可以提供与DM高速缓存相当的延迟水平，对关键信号路径上的附加逻辑电路的DM高速缓存电路进行最小修改，同时在低区域开销提供具有SA缓存类似的低功率操作错过率。地址掩码和最近使用的保存替换策略可以采用每行一个位开销。

10. 发明授权

US08578316B1 Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation 有权
公开(公告)号：US08578316B1
公开(公告)日：2013-11-05
申请号：US13607678
申请日：2012-09-08
申请人： Rajiv V. Joshi , Ajay N. Bhoj
发明人： Rajiv V. Joshi , Ajay N. Bhoj
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5018
摘要： A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

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