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1. 发明申请

US20140268534A1 METHODS OF ADDING DOPANTS TO CONDUCTIVE INTERCONNECT STRUCTURES IN SUBSTRATE TECHNOLOGIES AND STRUCTURES FORMED THEREBY 有权
标题翻译：将基质添加到基板技术中的导电互连结构的方法和形成的结构
公开(公告)号：US20140268534A1
公开(公告)日：2014-09-18
申请号：US13795042
申请日：2013-03-12
申请人： Rajen S. Sidhu , Mukul P. Renavikar , Sandeep B. Sane
发明人： Rajen S. Sidhu , Mukul P. Renavikar , Sandeep B. Sane
IPC分类号： H05K1/09 , C25D3/58 , H05K3/10
CPC分类号： C25D3/58 , C23C18/48 , C25D5/02 , H05K3/421 , H05K3/4644
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include forming an opening in a dielectric material of a package substrate, and then plating a conductive interconnect structure in the opening utilizing a plating process. The plating process may comprises a conductive metal and a dopant comprising between about 0.05 and 10 percent weight, wherein the dopant comprises at least one of magnesium, zirconium and zinc.
摘要翻译：描述了形成微电子封装结构的方法及由此形成的相关结构。这些方法和结构可以包括在封装衬底的电介质材料中形成开口，然后使用电镀工艺在开口中镀覆导电互连结构。电镀工艺可以包括导电金属和掺杂剂，其包含约0.05至10重量％的重量，其中掺杂剂包括镁，锆和锌中的至少一种。

2. 发明申请

US20150333022A1 CONTACT PADS FOR INTEGRATED CIRCUIT PACKAGES 有权
标题翻译：用于集成电路封装的接触垫
公开(公告)号：US20150333022A1
公开(公告)日：2015-11-19
申请号：US14280110
申请日：2014-05-16
申请人： Sven Albers , Georg Seidemann , Sonja Koller , Stephan Stoeckl , Shubhada H. Sahasrabudhe , Sandeep B. Sane
发明人： Sven Albers , Georg Seidemann , Sonja Koller , Stephan Stoeckl , Shubhada H. Sahasrabudhe , Sandeep B. Sane
IPC分类号： H01L23/00 , H01L23/498
CPC分类号： H01L24/05 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/141 , H01L2224/16238 , H01L2924/15311 , H01L2924/3511 , H05K1/111 , H05K3/3436 , H05K2201/0373
摘要： Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a substrate of an IC package, and may include a metal projection portion and a metal recess portion. Each of the metal projection portion and the metal recess portion may have a solder contact surface. The solder contact surface of the metal recess portion may be spaced away from the solder contact surface of the metal projection portion. Related devices and techniques are also disclosed herein, and other embodiments may be claimed.
摘要翻译：这里公开了与集成电路（IC）封装一起使用的接触焊盘。在一些实施例中，本文公开的接触垫可以设置在IC封装的基板上，并且可以包括金属突出部分和金属凹部。金属突出部和金属凹部中的每一个可以具有焊料接触表面。金属凹部的焊接接触表面可以与金属突出部的焊接接触表面间隔开。本文还公开了相关的设备和技术，并且可以要求保护其他实施例。

3. 发明授权

US08941236B2 Using collapse limiter structures between elements to reduce solder bump bridging 有权
标题翻译：使用元件之间的折叠限制器结构来减少焊料凸块桥接
公开(公告)号：US08941236B2
公开(公告)日：2015-01-27
申请号：US13631713
申请日：2012-09-28
申请人： Ameya Limaye , Richard J. Harries , Sandeep B. Sane
发明人： Ameya Limaye , Richard J. Harries , Sandeep B. Sane
IPC分类号： H01L23/48
CPC分类号： H01L23/49816 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2224/131 , H01L2224/16225 , H01L2224/81007 , H01L2224/81139 , H01L2224/8114 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2924/15311 , H01L2924/3511 , H01L2924/014 , H01L2224/81
摘要： Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface.Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.
摘要翻译：提供一种电子组件及其形成方法，包括具有第一表面的第一元件和具有第二表面的第二元件。在通过加热焊料凸块形成的第一和第二元件之间提供电连接。至少一个崩溃限制器结构耦合到第一和第二表面中的至少一个，其中至少一个崩溃限制器结构在至少两个电连接之间。

4. 发明授权

US09123732B2 Die warpage control for thin die assembly 有权
标题翻译：用于薄模组件的模翘曲控制
公开(公告)号：US09123732B2
公开(公告)日：2015-09-01
申请号：US13631612
申请日：2012-09-28
申请人： Sandeep B. Sane , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
发明人： Sandeep B. Sane , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/00
CPC分类号： H01L24/32 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/89 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/3213 , H01L2224/32225 , H01L2224/32501 , H01L2224/32505 , H01L2224/73253 , H01L2224/81007 , H01L2224/81193 , H01L2224/81815 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/161 , H01L2924/16251 , H01L2924/3511 , H01L2924/00 , H01L2924/014
摘要： Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
摘要翻译：控制模具翘曲，用于组装薄模具。在一个示例中，形成具有背面上的基板和在前侧层中的部件的装置。背衬层形成在衬底上，该层在加热器件时抵抗器件翘曲。该装置通过加热连接到基板。

5. 发明申请

US20110156254A1 MODIFIED CHIP ATTACH PROCESS 有权
标题翻译：改装芯片连接流程
公开(公告)号：US20110156254A1
公开(公告)日：2011-06-30
申请号：US13042239
申请日：2011-03-07
申请人： Sandeep B. Sane , Biju Chandran
发明人： Sandeep B. Sane , Biju Chandran
IPC分类号： H01L23/488
CPC分类号： H01L24/81 , H01L21/56 , H01L21/563 , H01L24/28 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/8191 , H01L2224/83102 , H01L2224/92125 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/16152 , H01L2924/00
摘要： A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
摘要翻译：一种用于组装用于半导体器件的封装的方法，其包括通过将所述管芯和所述衬底加热至所述焊料回流的温度，降低至所选择的环氧树脂将固化的温度，从而使包封期间的内部电介质层中的应力降低将液化环氧树脂加入到模具和基材中，并将模具和基材保持在环氧树脂固化一定时间的温度。

6. 发明授权

US06788859B1 Laminate substrate containing fiber optic cables 失效
标题翻译：含有光纤电缆的层压基板
公开(公告)号：US06788859B1
公开(公告)日：2004-09-07
申请号：US10286732
申请日：2002-10-31
申请人： Voya R. Markovich , Sandeep B. Sane , Sanjeev Sathe
发明人： Voya R. Markovich , Sandeep B. Sane , Sanjeev Sathe
IPC分类号： G02B644
CPC分类号： G02B6/43 , G02B6/3608 , G02B6/4471 , H05K1/0274 , H05K3/4602
摘要： A method and an article made by a method for embedding optical fibers into an organic laminate structure. The optical fiber cabling, along with its cladding, is placed upon a first laminate layer that includes a composite made of silica fillers and a frictionless material such as polytetrafluoroethylene (PTFE). Then a second layer of PTFE material with silica fillers and copper sheeting is placed on top of the PTFE with silica fillers composite. The PTFE material with silica fillers flows about the optical fibers at a temperature approximately fifty degrees above the PTFE with silica fillers material's melting point. This procedure completely encases the optical fibers within an opaque sheath.
摘要翻译：一种通过将光纤嵌入到有机层压结构中的方法制造的方法和制品。光纤布线及其包层放置在第一层压层上，第一层压层包括由二氧化硅填料制成的复合材料和诸如聚四氟乙烯（PTFE）的无摩擦材料。然后将具有二氧化硅填料和铜片的第二层PTFE材料放置在具有二氧化硅填料复合材料的PTFE的顶部上。具有二氧化硅填料的PTFE材料在具有二氧化硅填料材料的熔点的PTFE上方约五十度的温度下围绕光纤流动。该过程完全将光纤包裹在不透明的护套内。

7. 发明申请

US20170178987A1 WARPAGE CONTROLLED PACKAGE AND METHOD FOR SAME 有权
公开(公告)号：US20170178987A1
公开(公告)日：2017-06-22
申请号：US14971744
申请日：2015-12-16
申请人： Siddarth Kumar , Sandeep B. Sane , Shubhada H. Sahasrabudhe , Shalabh Tandon
发明人： Siddarth Kumar , Sandeep B. Sane , Shubhada H. Sahasrabudhe , Shalabh Tandon
IPC分类号： H01L23/16
CPC分类号： H01L23/562 , H01L23/16 , H01L23/49822 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/16227 , H01L2224/81815 , H01L2924/15311 , H01L2924/3511 , H01L2924/014 , H01L2924/00014
摘要： A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along the substrate. A plurality of electrical contacts extend between at least the device and the substrate. One or more counter moment elements are coupled with the substrate. The one or more counter moment elements include a passive configuration and a counter moment configuration. In the counter moment configuration the one or more counter moment elements are configured to apply a counter moment to the substrate to counteract the warped configuration. In the passive configuration the one or more counter moment elements are configured to apply a neutral counter moment less than the counter moment of the counter moment configuration.

8. 发明申请

US20140091470A1 DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY 有权
标题翻译：用于薄膜组件的DIE WARPAGE控制
公开(公告)号：US20140091470A1
公开(公告)日：2014-04-03
申请号：US13631612
申请日：2012-09-28
申请人： Sandeep B. Sane , Shandar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
发明人： Sandeep B. Sane , Shandar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
IPC分类号： H01L23/00
CPC分类号： H01L24/32 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/89 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/3213 , H01L2224/32225 , H01L2224/32501 , H01L2224/32505 , H01L2224/73253 , H01L2224/81007 , H01L2224/81193 , H01L2224/81815 , H01L2924/10253 , H01L2924/12042 , H01L2924/15311 , H01L2924/161 , H01L2924/16251 , H01L2924/3511 , H01L2924/00 , H01L2924/014
摘要： Die warpage is controlled for the assembly of thin dies. In one example, a device having a substrate on a back side and components in front side layers is formed. A backside layer is formed over the substrate, the layer resisting warpage of the device when the device is heated. The device is attached to a substrate by heating.
摘要翻译：控制模具翘曲，用于组装薄模具。在一个示例中，形成具有背面上的基板和在前侧层中的部件的装置。背衬层形成在衬底上，该层在加热器件时抵抗器件翘曲。该装置通过加热连接到基板。

9. 发明申请

US20090275175A1 MODIFIED CHIP ATTACH PROCESS 有权
标题翻译：改装芯片连接流程
公开(公告)号：US20090275175A1
公开(公告)日：2009-11-05
申请号：US12502088
申请日：2009-07-13
申请人： Sandeep B. Sane , Biju Chandran
发明人： Sandeep B. Sane , Biju Chandran
IPC分类号： H01L21/56
CPC分类号： H01L24/81 , H01L21/56 , H01L21/563 , H01L24/28 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/8121 , H01L2224/81815 , H01L2224/8191 , H01L2224/83102 , H01L2224/92125 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/16152 , H01L2924/00
摘要： A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time.
摘要翻译：一种用于组装用于半导体器件的封装的方法，其包括通过将所述管芯和所述衬底加热至所述焊料回流的温度，降低至所选择的环氧树脂将固化的温度，从而使包封期间的内部电介质层中的应力降低将液化环氧树脂加入到模具和基材中，并将模具和基材保持在环氧树脂固化一定时间的温度。

10. 发明授权

US07312527B2 Low temperature phase change thermal interface material dam 有权
标题翻译：低温相变热界面材料坝
公开(公告)号：US07312527B2
公开(公告)日：2007-12-25
申请号：US11305527
申请日：2005-12-16
申请人： Sandeep B. Sane , Nitin Deshpande , Chia-Pin Chiu
发明人： Sandeep B. Sane , Nitin Deshpande , Chia-Pin Chiu
IPC分类号： H01L23/34
CPC分类号： H01L23/4275 , H01L24/32 , H01L2224/73253 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01082 , H01L2924/0132 , H01L2924/14 , H01L2924/1433
摘要： A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.
摘要翻译：一种具有半导体封装的方法，装置和系统，包括封闭一定体积的热界面材料的热界面材料坝。

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