专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100006987A1 INTEGRATED CIRCUIT PACKAGE WITH EMI SHIELD 审中-公开
标题翻译：集成电路封装与EMI屏蔽
公开(公告)号：US20100006987A1
公开(公告)日：2010-01-14
申请号：US12169908
申请日：2008-07-09
申请人： Rajen Murugan , Kenneth R. Rhyner , Peter R. Harper , Souvik Mukherjee
发明人： Rajen Murugan , Kenneth R. Rhyner , Peter R. Harper , Souvik Mukherjee
IPC分类号： H01L23/552 , G06F17/50
CPC分类号： H01L23/552 , H01L24/48 , H01L2224/48091 , H01L2225/0651 , H01L2225/0652 , H01L2225/06527 , H01L2924/00014 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit (IC) device (200) includes an electronic substrate (201) having a plurality of layers (120) including at least one first electrically conductive layer and a lower surface dielectric layer. The IC device also includes an electrically conductive surface layer (126) disposed on the dielectric layer and coupled to a ground terminal (210) for the electronic substrate (201) for blocking electromagnetic interference (EMI). In the IC device, the conductive surface layer (126) includes an EMI shield region (204) over at least a portion of the dielectric layer. The EMI shield region (204) includes at least one solid area (206) and one or more adhesion areas (207) having a plurality of openings (208) arranged aperiodically in the adhesion areas (207).
摘要翻译：集成电路（IC）装置（200）包括具有包括至少一个第一导电层和下表面电介质层的多个层（120）的电子基板（201）。 IC器件还包括设置在电介质层上并耦合到用于电子衬底（201）的用于阻挡电磁干扰（EMI）的接地端子（210）的导电表面层（126）。在IC器件中，导电表面层（126）在电介质层的至少一部分上包括EMI屏蔽区域（204）。 EMI屏蔽区域（204）包括至少一个固体区域（206）和一个或多个粘附区域（207），其具有在粘附区域（207）中非周期地布置的多个开口（208）。

2. 发明申请

US20090166889A1 PACKAGED INTEGRATED CIRCUITS HAVING SURFACE MOUNT DEVICES AND METHODS TO FORM PACKAGED INTEGRATED CIRCUITS 审中-公开
标题翻译：具有表面安装器件的封装集成电路和形成包装集成电路的方法
公开(公告)号：US20090166889A1
公开(公告)日：2009-07-02
申请号：US11967844
申请日：2007-12-31
申请人： Rajen Murugan , Peter R. Harper , Mark Gerber
发明人： Rajen Murugan , Peter R. Harper , Mark Gerber
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L24/83 , H01L23/3128 , H01L23/49816 , H01L23/50 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/16 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/73204 , H01L2224/73265 , H01L2224/83102 , H01L2224/8385 , H01L2224/92125 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19106 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： Packaged integrated circuits having surface mount devices and methods to form the same are disclosed. A disclosed method comprises attaching an integrated circuit to a first side of a substrate, forming one or more first conductive elements on the substrate, attaching a surface mount device to a second side of the substrate via the first conductive elements, forming one or more second conductive elements on the second side of the substrate.
摘要翻译：公开了具有表面贴装装置的封装集成电路及其形成方法。所公开的方法包括将集成电路附接到衬底的第一侧，在衬底上形成一个或多个第一导电元件，经由第一导电元件将表面安装器件附接到衬底的第二侧，形成一个或多个第二在基板的第二面上的导电元件。

3. 发明申请

US20070244684A1 Method to model 3-D PCB PTH via 审中-公开
标题翻译： 3-D PCB PTH通道的建模方法
公开(公告)号：US20070244684A1
公开(公告)日：2007-10-18
申请号：US11405242
申请日：2006-04-17
申请人： Rajen Murugan , Jimmy Pike , Abeye Teshome
发明人： Rajen Murugan , Jimmy Pike , Abeye Teshome
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , H05K1/0216 , H05K1/0237 , H05K3/0005 , H05K3/429 , H05K2201/09327
摘要： A methodology may be used that takes into account the inductive coupling of current transients on the power rails of a printed circuit board (PCB) that may be coupled to the barrel of a via. By taking into account the coupling of the current transients on the power rails of the PCB, more accurate and realistic modeling results may be obtained. Inductive coupling of the current transients from the power rails may be more pronounced at higher frequencies and may be additive for more layer transitions (e.g., more via transitions) of the PCB.
摘要翻译：可以使用考虑到可以耦合到通孔的筒的印刷电路板（PCB）的电源轨上的电流瞬变的电感耦合的方法。通过考虑PCB上电源线上的电流瞬变的耦合，可以获得更精确和逼真的建模结果。来自电源轨的电流瞬变的感性耦合可能在较高频率下更为显着，并且可能对于PCB的更多层转变（例如更多的经由转变）而言是相加的。

4. 发明授权

US07889785B2 Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budget 有权
标题翻译：用于量化符号间干扰抖动对定时偏差预算的贡献的方法，系统和装置
公开(公告)号：US07889785B2
公开(公告)日：2011-02-15
申请号：US11830836
申请日：2007-07-30
申请人： Rajen Murugan , Michael Greim
发明人： Rajen Murugan , Michael Greim
IPC分类号： H03H7/30
CPC分类号： G01R31/31709 , G01R31/31715 , G01R31/31725 , H04L7/0054 , H04L7/10 , H04L25/0212
摘要： An apparatus, method and system are provided for quantifying communication channel intersymbol interference jitter effect contribution to timing skew. In general, lossy and lossless characteristics of the communication channel are preferably obtained and an output signal of the communication channel is sampled. From the sampled output signal and the lossy characteristics of the communication channel, an input signal may be derived. Using the lossless characteristics of the communication channel, the derived input signal and the sampled output signal, a value indicating the contribution of intersymbol interference jitter effect on timing skew budget for a selection communication channel may be obtained.
摘要翻译：提供了一种设备，方法和系统，用于量化通信信道码间干扰抖动对定时偏移的影响。通常，优选地获得通信信道的有损和无损特征，并对通信信道的输出信号进行采样。从采样输出信号和通信信道的有损特性可以得出输入信号。使用通信信道的无损特性，可以获得导出的输入信号和采样的输出信号，表示对于选择通信信道，表示符号间干扰抖动对定时偏差预算的影响的值。

5. 发明申请

US20050231927A1 Method, system and apparatus for controlled impedance at transitional plated-through hole via sites using barrel inductance minimization 审中-公开
标题翻译：使用圆筒电感最小化的过渡电镀通孔的控制阻抗的方法，系统和装置
公开(公告)号：US20050231927A1
公开(公告)日：2005-10-20
申请号：US10828449
申请日：2004-04-20
申请人： Jinsaku Masuyama , Rajen Murugan
发明人： Jinsaku Masuyama , Rajen Murugan
IPC分类号： H05K1/02 , H05K1/11 , H05K3/42 , H05K7/06
CPC分类号： H05K1/115 , H05K1/0237 , H05K3/429 , H05K2201/09536 , H05K2201/09645 , Y10T29/49124
摘要： A system, apparatus and method for controlled impedance at transitional via sites using barrel inductance minimization are provided. In one embodiment, one or more sidewalls of a via barrel are preferably processed such that conductive material disposed thereon is selectively removed thereby forming an inner-via trace connecting one or more conductive traces and/or pads on a first substrate layer to one or more conductive traces and/or pads on a second substrate layer. Removal of conductive material from a sidewall of the via barrel is done in a manner such that an inner-via trace traveling from a first surface to a second surface of one or more substrate layers possesses at least one electrical characteristic substantially approximating a corresponding electrical characteristic of those structures to which the inner-via trace is connected.
摘要翻译：提供了一种使用筒电感最小化的过渡通过位置处的受控阻抗的系统，装置和方法。在一个实施例中，通孔筒的一个或多个侧壁优选地被加工成使得选择性地去除布置在其上的导电材料，从而形成将第一衬底层上的一个或多个导电迹线和/或焊盘连接到一个或多个导电迹线和/或第二基底层上的焊盘。从通孔筒的侧壁去除导电材料以这样的方式进行，使得从一个或多个基底层的第一表面到第二表面行进的内部通路迹线具有至少一个电特性，其基本上接近相应的电特性内部通孔迹线连接到的那些结构。

6. 发明申请

US20070217168A1 Method, System And Apparatus For Controlled Impedance At Transitional Plated-Through Hole Via Sites Using Barrel Inductance Minimization 审中-公开
标题翻译：用于控制阻抗的方法，系统和装置通过使用桶式电感最小化的位置在过渡电镀通孔
公开(公告)号：US20070217168A1
公开(公告)日：2007-09-20
申请号：US11752032
申请日：2007-05-22
申请人： Jinsaku Masuyama , Rajen Murugan
发明人： Jinsaku Masuyama , Rajen Murugan
IPC分类号： H05K7/06
CPC分类号： H05K1/115 , H05K1/0237 , H05K3/429 , H05K2201/09536 , H05K2201/09645 , Y10T29/49124
摘要： A system, apparatus and method for controlled impedance at transitional via sites using barrel inductance minimization are provided. In one embodiment, one or more sidewalls of a via barrel are preferably processed such that conductive material disposed thereon is selectively removed thereby forming an inner-via trace connecting one or more conductive traces and/or pads on a first substrate layer to one or more conductive traces and/or pads on a second substrate layer. Removal of conductive material from a sidewall of the via barrel is done in a manner such that an inner-via trace traveling from a first surface to a second surface of one or more substrate layers possesses at least one electrical characteristic substantially approximating a corresponding electrical characteristic of those structures to which the inner-via trace is connected.
摘要翻译：提供了一种使用筒电感最小化的过渡通过位置处的受控阻抗的系统，装置和方法。在一个实施例中，通孔筒的一个或多个侧壁优选地被加工成使得选择性地去除布置在其上的导电材料，从而形成将第一衬底层上的一个或多个导电迹线和/或焊盘连接到一个或多个导电迹线和/或第二基底层上的焊盘。从通孔筒的侧壁去除导电材料以这样的方式进行，使得从一个或多个基底层的第一表面到第二表面行进的内部通孔迹线具有至少一个电特性，其基本上接近相应的电特性内部通孔迹线连接到的那些结构。

7. 发明授权

US07680226B2 Minimizing dynamic crosstalk-induced jitter timing skew 有权
标题翻译：最小化动态串扰引起的抖动定时偏移
公开(公告)号：US07680226B2
公开(公告)日：2010-03-16
申请号：US11088544
申请日：2005-03-24
申请人： Rajen Murugan , Girish K. Singh
发明人： Rajen Murugan , Girish K. Singh
IPC分类号： H03D1/04
CPC分类号： H04B3/32 , H03K5/156
摘要： A digital signal waveform receiving circuit may be processed by a non-linear adaptive canonical correlation analysis circuit that may quantify and minimize crosstalk-induced jitter timing skew for improving set-up and hold timing margins of data streams on the receiving circuit. A non-linear adaptive canonical correlation analysis circuit may be placed between an incoming digital signal from a serial link and a PHY receiving layer of an information handling system 100. The PHY receiving layer of the information handling system may be coupled to the non-linear adaptive canonical correlation analysis circuit or may be coupled to the digital signal. This coupling selection may be automatically programmed depending on received signal cross-talk-induced jitter timing skew or may be programmed by a user of the information handling system.
摘要翻译：数字信号波形接收电路可以由非线性自适应规范相关分析电路进行处理，该电路可以量化并最小化串扰引起的抖动定时偏差，以改善接收电路上的数据流的建立和保持定时裕度。可以将非线性自适应规范相关分析电路放置在来自串行链路的输入数字信号和信息处理系统100的PHY接收层之间。信息处理系统的PHY接收层可以耦合到非线性自适应规范相关分析电路或者可以耦合到数字信号。该耦合选择可以根据接收到的信号串扰引起的抖动定时偏差而被自动编程，或者可由信息处理系统的用户编程。

8. 发明申请

US20090034665A1 Method, System and Apparatus for Quantifying the Contribution of Inter-Symbol Interference Jitter on Timing Skew Budget 有权
标题翻译：用于量化符号间干扰抖动对时序偏移预算贡献的方法，系统和装置
公开(公告)号：US20090034665A1
公开(公告)日：2009-02-05
申请号：US11830836
申请日：2007-07-30
申请人： Rajen Murugan , Michael Greim
发明人： Rajen Murugan , Michael Greim
IPC分类号： H03D1/04
CPC分类号： G01R31/31709 , G01R31/31715 , G01R31/31725 , H04L7/0054 , H04L7/10 , H04L25/0212
摘要： An apparatus, method and system are provided for quantifying communication channel intersymbol interference jitter effect contribution to timing skew. In general, lossy and lossless characteristics of the communication channel are preferably obtained and an output signal of the communication channel is sampled. From the sampled output signal and the lossy characteristics of the communication channel, an input signal may be derived. Using the lossless characteristics of the communication channel, the derived input signal and the sampled output signal, a value indicating the contribution of intersymbol interference jitter effect on timing skew budget for a selection communication channel may be obtained.
摘要翻译：提供了一种设备，方法和系统，用于量化通信信道码间干扰抖动对定时偏移的影响。通常，优选地获得通信信道的有损和无损特征，并对通信信道的输出信号进行采样。从采样输出信号和通信信道的有损特性可以得出输入信号。使用通信信道的无损特性，可以获得导出的输入信号和采样的输出信号，表示对于选择通信信道，表示码间干扰抖动对定时偏差预算的影响的值。

9. 发明申请

US20050125175A1 Method, system and apparatus for quantifying the contribution of inter-symbol interference jitter on timing skew budget 有权
标题翻译：用于量化符号间干扰抖动对定时偏差预算的贡献的方法，系统和装置
公开(公告)号：US20050125175A1
公开(公告)日：2005-06-09
申请号：US10729625
申请日：2003-12-05
申请人： Rajen Murugan , Michael Greim
发明人： Rajen Murugan , Michael Greim
IPC分类号： G01R31/317 , G01R13/00 , G01R29/26 , G06F19/00
CPC分类号： G01R31/31709 , G01R31/31715 , G01R31/31725 , H04L7/0054 , H04L7/10 , H04L25/0212
摘要： An apparatus, method and system are provided for quantifying communication channel intersymbol interference jitter effect contribution to timing skew. In general, lossy and lossless characteristics of the communication channel are preferably obtained and an output signal of the communication channel is sampled. From the sampled output signal and the lossy characteristics of the communication channel, an input signal may be derived. Using the lossless characteristics of the communication channel, the derived input signal and the sampled output signal, a value indicating the contribution of intersymbol interference jitter effect on timing skew budget for a selection communication channel may be obtained.
摘要翻译：提供了一种设备，方法和系统，用于量化通信信道码间干扰抖动对定时偏移的影响。通常，优选地获得通信信道的有损和无损特征，并对通信信道的输出信号进行采样。从采样输出信号和通信信道的有损特性可以得出输入信号。使用通信信道的无损特性，可以获得导出的输入信号和采样的输出信号，表示对于选择通信信道，表示符号间干扰抖动对定时偏差预算的影响的值。

10. 发明授权

US07577203B2 Minimizing non-deterministic noise by using wavelet transform 有权
标题翻译：通过使用小波变换来最小化非确定性噪声
公开(公告)号：US07577203B2
公开(公告)日：2009-08-18
申请号：US11089384
申请日：2005-03-24
申请人： Rajen Murugan , Bhavesh A. Patel
发明人： Rajen Murugan , Bhavesh A. Patel
IPC分类号： H04B1/66 , H03D1/04 , H04B3/46 , H03H7/30
CPC分类号： H04L25/03012 , H04L25/03159
摘要： A wavelet transform noise minimization circuit comprises a differential receiver, a voltage comparator, a wavelet transform circuit, an electrical idle (EI) detector circuit, a phase interpolator, a phase-locked-loop (PLL), and a reference clock buffer. The wavelet transform noise minimization circuit may be beneficially applied wherever there is non-deterministic (e.g., random) noise in the PHY layer during an electrical idle state. The wavelet transform noise minimization circuit may be used to improve noise margin during an electrical idle state, and/or reduce the occurrence of false activation of a PHY layer when in the electrical idle state.
摘要翻译：小波变换噪声最小化电路包括差分接收器，电压比较器，小波变换电路，电空闲（EI）检测器电路，相位内插器，锁相环（PLL）和参考时钟缓冲器。无论在电空闲状态下在PHY层中存在非确定性（例如随机）噪声的情况下，小波变换噪声最小化电路都可以被有益地应用。可以使用小波变换噪声最小化电路来在电空闲状态期间改善噪声容限，和/或在电空闲状态时减少PHY层的错误激活的发生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式