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1. 发明申请

US20060168456A1 Method and apparatus to generate circuit energy models with multiple clock gating inputs 失效
标题翻译：用多个时钟门控输入产生电路能量模型的方法和装置
公开(公告)号：US20060168456A1
公开(公告)日：2006-07-27
申请号：US11044568
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.
摘要翻译：提供了一种方法，计算机程序和装置，用于使用多个时钟选通输入来产生用于宏的电路能量模型。电路能量模型用于估计系统功耗。本发明使得能够为包含多个时钟选通输入的宏创建电路能量模型。能量表基于宏的输入开关因子和时钟激活百分比创建。通过在模拟期间打开和关闭多个时钟门控输入来产生时钟激活百分比。这些能量表是从最小数量的功率模拟产生的。通过使用时钟激活百分比作为参数，产生精确的功率估计。

2. 发明申请

US20060167673A1 Method and apparatus to generate circuit energy models for macros containing internal clock gating 失效
标题翻译：用于生成包含内部时钟门控的宏的电路能量模型的方法和装置
公开(公告)号：US20060167673A1
公开(公告)日：2006-07-27
申请号：US11044599
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro containing internal clock gating. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain internal clock gating and multiple clock gating inputs. To achieve accurate power estimates a voltage supply is connected to each clock activate signal. Energy tables are then created based upon the macro's input switching factor percentage and clock activation percentage. These power tables are generated from a minimum number of power simulations. By incorporating internally generated clock activate signals into the power estimations the macro energy tables are much more accurate.
摘要翻译：提供了一种用于产生用于包含内部时钟门控的宏的电路能量模型的方法，计算机程序和装置。电路能量模型用于估计系统功耗。本发明使得能够为包含内部时钟门控和多个时钟门控输入的宏创建电路能量模型。为了实现精确的功率估计，电源连接到每个时钟激活信号。然后根据宏的输入切换因子百分比和时钟激活百分比创建能量表。这些功率表是从最小数量的功率模拟产生的。通过将内部生成的时钟激活信号并入功率估计中，宏能量表更准确。

3. 发明申请

US20060190856A1 Method and apparatus to generate circuit energy models with clock gating 失效
标题翻译：用时钟门控生成电路能量模型的方法和装置
公开(公告)号：US20060190856A1
公开(公告)日：2006-08-24
申请号：US11044597
申请日：2005-01-27
申请人： Rajat Chaudhry , James Neely , Daniel Stasiak
发明人： Rajat Chaudhry , James Neely , Daniel Stasiak
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain clock gating inputs. Power tables are created based upon the macro's input switching factor percentage and the clock activation percentage. These power tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate energy tables are produced.
摘要翻译：提供了一种方法，计算机程序和装置，用于使用时钟门控输入来产生用于宏的电路能量模型。电路能量模型用于估计系统功耗。本发明使得能够为包含时钟门控输入的宏创建电路能量模型。功率表基于宏的输入开关因子百分比和时钟激活百分比创建。这些功率表是从最小数量的功率模拟产生的。通过使用时钟激活百分比作为参数，产生精确的能量表。

4. 发明申请

US20050159907A1 Method and apparatus for VLSI clock gated power estimation using LCB counts 审中-公开
标题翻译：使用LCB计数的VLSI时钟选通功率估计的方法和装置
公开(公告)号：US20050159907A1
公开(公告)日：2005-07-21
申请号：US10759936
申请日：2004-01-16
申请人： Rajat Chaudhry , Brian Flachs , Daniel Stasiak
发明人： Rajat Chaudhry , Brian Flachs , Daniel Stasiak
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5036
摘要： A method, an apparatus, and a computer program are provided for modeling algorithm for power consumption with improved accuracy. The improved model allows for variable operation of Local Clock Buffers (LCBs), which consume significant amounts power. Also, the amount of power consumed by each LCB can be varied. These variations of operation of LCBs and power consumption by LCBs allows for a more realistic model of operation of a given circuit or macro instead of the traditional “worst-case scenario” of power consumption.
摘要翻译：提供了一种方法，装置和计算机程序，用于提高精度的功耗建模算法。改进的模型允许本地时钟缓冲器（LCB）的可变操作，其消耗大量的功率。此外，每个LCB消耗的功率量可以变化。 LCB的这些操作变化和LCB的功耗允许给定电路或宏的更实际的操作模型，而不是传统的“最坏情况”的功耗。

5. 发明申请

US20050278664A1 Predicting power consumption for a chip 审中-公开
标题翻译：预测芯片的功耗
公开(公告)号：US20050278664A1
公开(公告)日：2005-12-15
申请号：US10855725
申请日：2004-05-27
申请人： Rajat Chaudhry , Sang Dhong , Stephen Posluszny , Daniel Stasiak
发明人： Rajat Chaudhry , Sang Dhong , Stephen Posluszny , Daniel Stasiak
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： A method, an apparatus, and a computer program are provided for predicting power consumption for chip. The model for predicting power consumptions is modified so at to provide a high degree of accuracy with a minimal amount of computing time. Traditionally, when modeling a chip, a vast amount of time and computer resources were required to predict power consumption. Techniques required less time and less computer power, but the accuracy also decreased. However, by breaking down a chip into macros and developing energy rules for each macro, simple techniques can be employed to accurately predict power consumption under real world conditions with a minimal amount of time and computing power.
摘要翻译：提供了一种用于预测芯片功耗的方法，装置和计算机程序。修改用于预测功耗的模型，以便以最小的计算时间提供高精度。传统上，当对芯片建模时，需要大量的时间和计算机资源来预测功耗。技术需要更少的时间和更少的计算机功率，但精度也降低了。然而，通过将芯片分解成宏并为每个宏开发能量规则，可以采用简单的技术来以最小的时间和计算能力精确地预测现实世界条件下的功耗。

6. 发明申请

US20070250798A1 METHOD AND APPARATUS IN LOCATING CLOCK GATING OPPORTUNITIES WITHIN A VERY LARGE SCALE INTEGRATION CHIP DESIGN 失效
标题翻译：在非常大的规模集成芯片设计中定位时钟机会的方法和设备
公开(公告)号：US20070250798A1
公开(公告)日：2007-10-25
申请号：US11380126
申请日：2006-04-25
申请人： RAJAT CHAUDHRY , Tilman Gloekler , Daniel Stasiak , Todd Swanson
发明人： RAJAT CHAUDHRY , Tilman Gloekler , Daniel Stasiak , Todd Swanson
IPC分类号： G06F17/50 , G06F19/00 , G06F17/18 , G06F15/00
CPC分类号： G06F17/5031
摘要： A computer implemented method, apparatus, and computer usable program code for generating statistics for a set of components in a computer chip. An exemplary computer implemented method includes identifying the set of components in the computer chip. The set of components include those components which are not clock gated. The exemplary method also includes generating statistics for the set of components. The statistics are related to clock gating testing to identify whether one or more components of the set of components can be clock gated.
摘要翻译：一种计算机实现的方法，装置和计算机可用程序代码，用于生成计算机芯片中的一组组件的统计。示例性的计算机实现的方法包括识别计算机芯片中的组件集合。这些组件包括不是时钟门控的组件。该示例性方法还包括生成该组组件的统计信息。这些统计信息与时钟门控测试相关，以确定组件组中的一个或多个组件是否可以进行时钟门控。

7. 发明申请

US20070130549A1 Clock-gating through data independent logic 失效
标题翻译：通过数据独立逻辑进行时钟门控
公开(公告)号：US20070130549A1
公开(公告)日：2007-06-07
申请号：US11295936
申请日：2005-12-07
申请人： Cynthia Eisner , Harm Hofstee , Alexander Itskovich , Daniel Stasiak
发明人： Cynthia Eisner , Harm Hofstee , Alexander Itskovich , Daniel Stasiak
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Given a function F of a circuit having a data latching device and a feedback loop feeding an output Q of the device into logic which feeds the device, a method includes extracting at least one data independent case and clock-gating the device with the at least one data independent case. The method also includes eliminating the feedback loop if function F depends only on Q with a positive polarity or leaving the feedback loop if function F depends on Q in both positive and negative polarities.
摘要翻译：给定具有数据锁存装置的电路的功能F和将装置的输出端Q馈送给装置的逻辑的反馈环路，一种方法包括提取至少一个与数据无关的情况，并且至少具有至少一个数据锁定装置的时钟选通装置一个数据独立的情况。该方法还包括消除反馈回路，如果功能F仅取决于具有正极性的Q或离开反馈回路，如果功能F取决于正极和负极性的Q。

8. 发明申请

US20060123261A1 Deep power saving by disabling clock distribution without separate clock distribution for power management logic 有权
标题翻译：通过禁用时钟分配，无需电源管理逻辑的单独时钟分配即可实现深度省电
公开(公告)号：US20060123261A1
公开(公告)日：2006-06-08
申请号：US11002551
申请日：2004-12-02
申请人： Mack Riley , Daniel Stasiak , Michael Wang , Stephen Weitzel
发明人： Mack Riley , Daniel Stasiak , Michael Wang , Stephen Weitzel
IPC分类号： G06F9/00
CPC分类号： G06F1/3203 , G06F1/3237 , Y02D10/128
摘要： An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.
摘要翻译：提供了一种装置，方法和计算机程序来禁止时钟分配。在微处理器中，时钟分配系统可以占用大量的功耗。然而，禁用时钟分配系统是困难的，因为通常需要用于控制逻辑的单独时钟。因此，可以采用组合逻辑来中断时钟分配，并且允许处理器被唤醒而不需要单独的时钟。

9. 发明申请

US20060119445A1 Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic 有权
标题翻译：在功率管理逻辑没有单独的时钟分配的情况下，在深省电状态下关闭PLLS的方法
公开(公告)号：US20060119445A1
公开(公告)日：2006-06-08
申请号：US11002559
申请日：2004-12-02
申请人： Mack Riley , Daniel Stasiak , Michael Wang , Stephen Weitzel
发明人： Mack Riley , Daniel Stasiak , Michael Wang , Stephen Weitzel
IPC分类号： H03B1/00
CPC分类号： G06F1/04 , G06F1/3203 , G06F1/3237 , H03L7/06 , Y02D10/126 , Y02D10/128 , Y10S331/02
摘要： An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.
摘要翻译：提供了一种设备，方法和计算机程序来对相位锁定环路（PLL）进行门控。在微处理器中，时钟分配系统可以占用大量的功耗。然而，门控门限是困难的，因为控制逻辑需要单独的时钟，因为PLL需要定时重新获取相位/频率锁定。因此，可以采用锁定检测逻辑来允许PLL重新获取相位/频率锁定。此外，可以采用来自外部设备和处理器的信号来门控PLL，并且允许处理器被唤醒而无需单独的时钟。

10. 发明申请

US20050261866A1 Thermal protection for a VLSI chip through reduced c4 usage 审中-公开
标题翻译：通过减少c4的使用，对VLSI芯片进行热保护
公开(公告)号：US20050261866A1
公开(公告)日：2005-11-24
申请号：US10850401
申请日：2004-05-20
申请人： David Boerstler , Hiroki Kihara , Robert Putney , Daniel Stasiak , Michael Wang
发明人： David Boerstler , Hiroki Kihara , Robert Putney , Daniel Stasiak , Michael Wang
IPC分类号： G01R31/26 , G01K7/01 , G01R31/28 , G06F15/00
CPC分类号： G01K7/01
摘要： The present invention provides for determining a temperature in a chip. A voltage across a thermal diode is generated. It is then determined whether the voltage across the first thermal diode exceeds a threshold value. The voltage is correlated with a range of values. The determination of whether the voltage across the thermal diode exceeds the threshold value is correlated with the correlation of the voltage with a range of values. Through the use of voltage level sensors, the use of C4 input/output pins are avoided.
摘要翻译：本发明提供用于确定芯片中的温度。产生热二极管两端的电压。然后确定第一热二极管两端的电压是否超过阈值。电压与值的范围相关。确定热二极管上的电压是否超过阈值与电压与一定范围的值的相关性相关。通过使用电压电平传感器，可以避免使用C4输入/输出引脚。

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