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1. 发明申请

US20110309357A1 MEASURING APPARATUS 有权
标题翻译：测量装置
公开(公告)号：US20110309357A1
公开(公告)日：2011-12-22
申请号：US12962658
申请日：2010-12-08
申请人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
发明人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
IPC分类号： H01L25/07
CPC分类号： G01B7/18 , G01L1/18 , G01L1/2206 , H01L2224/16145
摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.
摘要翻译：提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。第一电路层设置在第一表面上。第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。第二电路层设置在第二表面上。

2. 发明授权

US08502224B2 Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor 有权
标题翻译：包括具有硅通孔，加热器和应力传感器的芯片的测量装置
公开(公告)号：US08502224B2
公开(公告)日：2013-08-06
申请号：US12962658
申请日：2010-12-08
申请人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
发明人： Ra-Min Tain , John H. Lau , Ming-Che Hsieh , Wei Li , Ming-Ji Dai
IPC分类号： H01L23/58
CPC分类号： G01B7/18 , G01L1/18 , G01L1/2206 , H01L2224/16145
摘要： A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.
摘要翻译：提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。第一电路层设置在第一表面上。第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。第二电路层设置在第二表面上。

3. 发明授权

US08456017B2 Filled through-silicon via with conductive composite material 有权
标题翻译：用导电复合材料填充硅通孔
公开(公告)号：US08456017B2
公开(公告)日：2013-06-04
申请号：US13174794
申请日：2011-07-01
申请人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
发明人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/486 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11009 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16225 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1434 , H01L2924/3511 , H01L2924/01046 , H01L2924/01079 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.
摘要翻译：通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是降低了通硅通孔的导热性。

4. 发明申请

US20120273939A1 FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF 有权
标题翻译：通过硅填充硅及其制造方法
公开(公告)号：US20120273939A1
公开(公告)日：2012-11-01
申请号：US13174794
申请日：2011-07-01
申请人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
发明人： Ming-Ji Dai , Heng-Chieh Chien , Ming-Che Hsieh , Jui-Feng Hung , Ra-Min Tain , John H. Lau
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L21/486 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/11009 , H01L2224/13082 , H01L2224/13147 , H01L2224/13155 , H01L2224/14181 , H01L2224/16225 , H01L2224/94 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/10329 , H01L2924/12042 , H01L2924/1421 , H01L2924/1434 , H01L2924/3511 , H01L2924/01046 , H01L2924/01079 , H01L2224/03 , H01L2224/11 , H01L2224/05552 , H01L2924/00
摘要： By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.
摘要翻译：通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是降低了通硅通孔的导热性。

5. 发明申请

US20120135547A1 FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS 有权
标题翻译：半导体器件的制造方法和测试方法和机械完整性测试装置
公开(公告)号：US20120135547A1
公开(公告)日：2012-05-31
申请号：US13023545
申请日：2011-02-09
申请人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
发明人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
IPC分类号： H01L21/66 , G01N3/00 , G01N3/20
CPC分类号： H01L22/12 , G01N19/04 , H01L2224/16
摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.
摘要翻译：提供了半导体器件和机械完整性测试装置的制造方法和测试方法。一种物体包括晶片，绝缘层和多个导电柱。晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。在机械完整性测试中，在第一盲孔中的导电柱合格之后，芯片区域中的导电柱电连接到元件。

6. 发明授权

US08397584B2 Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus 有权
标题翻译：半导体器件及机械完整性检测仪器的制作方法及测试方法
公开(公告)号：US08397584B2
公开(公告)日：2013-03-19
申请号：US13023545
申请日：2011-02-09
申请人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
发明人： Ming-Che Hsieh , John H. Lau , Ra-Min Tain
IPC分类号： G01N3/00 , G01N3/20
CPC分类号： H01L22/12 , G01N19/04 , H01L2224/16
摘要： A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.
摘要翻译：提供了半导体器件和机械完整性测试装置的制造方法和测试方法。一种物体包括晶片，绝缘层和多个导电柱。晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。在机械完整性测试中，在第一盲孔中的导电柱被限定之后，芯片区域中的导电柱电连接到元件。

7. 发明申请

US20120280385A1 ELECTRONIC DEVICE PACKAGING STRUCTURE 有权
标题翻译：电子设备包装结构
公开(公告)号：US20120280385A1
公开(公告)日：2012-11-08
申请号：US13411639
申请日：2012-03-05
申请人： Ra-Min Tain , Ming-Ji Dai , John H. Lau
发明人： Ra-Min Tain , Ming-Ji Dai , John H. Lau
IPC分类号： H01L23/48
CPC分类号： H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/45 , H01L24/48 , H01L29/4175 , H01L29/41766 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/06181 , H01L2224/06505 , H01L2224/13 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/73253 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/10253 , H01L2924/00 , H01L2224/48744 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.
摘要翻译：提供一种电子设备包装结构。半导体器件包括半导体基底，发射极，集电极和栅极。发射极和栅极设置在半导体基底的第一表面上。集电体设置在半导体基底的第二表面上。第一钝化层位于围绕栅极的半导体基底的第一表面上。第一导电焊盘设置在第一钝化层上。第二导电焊盘设置在第二表面上的集电器上。至少一个导电贯通孔结构穿透第一钝化层，半导体基底的第一和第二表面以及集电器，以电连接第一和第二导电焊盘。

8. 发明申请

US20120153454A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120153454A1
公开(公告)日：2012-06-21
申请号：US13103107
申请日：2011-05-09
申请人： Chun-Kai Liu , John H. Lau , Ming-Ji Dai , Ra-Min Tain
发明人： Chun-Kai Liu , John H. Lau , Ming-Ji Dai , Ra-Min Tain
IPC分类号： H01L23/36
CPC分类号： H01L23/38 , H01L21/76898 , H01L23/481 , H01L23/53276 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589
摘要： A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.
摘要翻译：一种半导体器件，包括硅衬底，多个硅纳米线簇，第一电路层和第二电路层。硅衬底具有第一表面，与第一表面相对的第二表面和多个通孔。硅纳米线簇分别设置在硅衬底的通孔中。第一电路层设置在第一表面上并连接到硅纳米线簇。第二电路层设置在第二表面上并连接到硅纳米线簇。

9. 发明授权

US08519524B1 Chip stacking structure and fabricating method of the chip stacking structure 有权
标题翻译：芯片堆叠结构和芯片堆叠结构的制造方法
公开(公告)号：US08519524B1
公开(公告)日：2013-08-27
申请号：US13586890
申请日：2012-08-16
申请人： Sheng-Tsai Wu , John H. Lau , Heng-Chieh Chien , Ra-Min Tain , Ming-Ji Dai , Yu-Lin Chao
发明人： Sheng-Tsai Wu , John H. Lau , Heng-Chieh Chien , Ra-Min Tain , Ming-Ji Dai , Yu-Lin Chao
IPC分类号： H01L23/02
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L2221/68327 , H01L2221/68345 , H01L2224/0345 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13014 , H01L2224/13082 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/1624 , H01L2224/17104 , H01L2224/81193 , H01L2224/94 , H01L2924/00013 , H01L2924/00014 , H01L2924/15151 , H01L2924/15311 , H01L2924/01074 , H01L2224/03 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599 , H01L2224/05552
摘要： A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.
摘要翻译：提供了包括载体，第一再分布层，第二再分配层，至少一个第一芯片，至少一个第二芯片和至少一个导体的芯片堆叠结构。载体具有彼此相对的第一表面和第二表面。载体具有至少一个通孔。第一和第二再分布层分别设置在载体的第一和第二表面上。第一和第二芯片设置在载体的第一和第二表面上，并分别与第一和第二再分配层电连接。导体设置在第一和第二芯片之一上。导体设置在通孔中。第一和第二芯片由导体电连接。在导体和围绕通孔的载体的内壁之间形成间隙。

10. 发明授权

US08674491B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08674491B2
公开(公告)日：2014-03-18
申请号：US13103107
申请日：2011-05-09
申请人： Chun-Kai Liu , John H. Lau , Ming-Ji Dai , Ra-Min Tain
发明人： Chun-Kai Liu , John H. Lau , Ming-Ji Dai , Ra-Min Tain
IPC分类号： H01L23/02
CPC分类号： H01L23/38 , H01L21/76898 , H01L23/481 , H01L23/53276 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589
摘要： A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.
摘要翻译：一种半导体器件，包括硅衬底，多个硅纳米线簇，第一电路层和第二电路层。硅衬底具有第一表面，与第一表面相对的第二表面和多个通孔。硅纳米线簇分别设置在硅衬底的通孔中。第一电路层设置在第一表面上并连接到硅纳米线簇。第二电路层设置在第二表面上并连接到硅纳米线簇。

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