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1. 发明申请

US20100052110A1 SEMICONDUCTOR DEVICE COMPRISING A CARBON-BASED MATERIAL FOR THROUGH HOLE VIAS 有权
标题翻译：包含通过孔VIAS的碳基材料的半导体器件
公开(公告)号：US20100052110A1
公开(公告)日：2010-03-04
申请号：US12505098
申请日：2009-07-17
申请人： Robert Seidel , Frank Feustel , Ralf Richter
发明人： Robert Seidel , Frank Feustel , Ralf Richter
IPC分类号： H01L23/48 , H01L21/98 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/53276 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/1305 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.
摘要翻译：在半导体器件中，可以基于含碳材料形成延伸穿过器件的衬底的通孔，从而与高温工艺相比具有优异的兼容性，同时与掺杂的半导体材料相比提供优异的电性能，类似。因此，在一些说明性实施例中，通孔过孔可以在用于形成关键电路元件的任何工艺步骤之前形成，从而基本上避免了通孔通孔结构与对应的半导体器件的器件级别的任何干扰。因此，可以实现高效率的三维集成方案。

2. 发明申请

US20080265426A1 SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含电气连接的半导体结构及其形成方法
公开(公告)号：US20080265426A1
公开(公告)日：2008-10-30
申请号：US11943820
申请日：2007-11-21
申请人： Robert Seidel , Ralf Richter , Frank Feustel
发明人： Robert Seidel , Ralf Richter , Frank Feustel
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/7684 , H01L21/7682 , H01L21/76829 , H01L21/76885
摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.
摘要翻译：一种形成半导体结构的方法包括提供包括第一材料层的衬底。在第一材料层上形成保护层。在第一材料层和保护层中形成至少一个开口。在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。执行平面化处理以去除开口外部的第二材料层的部分。在平坦化处理期间，保护层的至少一部分不被去除。执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

3. 发明申请

US20090181537A1 SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含电气连接的半导体结构及其形成方法
公开(公告)号：US20090181537A1
公开(公告)日：2009-07-16
申请号：US12411873
申请日：2009-03-26
申请人： ROBERT SEIDEL , Ralf Richter , Frank Feustel
发明人： ROBERT SEIDEL , Ralf Richter , Frank Feustel
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/7682 , H01L21/76829 , H01L21/76885
摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.
摘要翻译：一种形成半导体结构的方法包括提供包括第一材料层的衬底。在第一材料层上形成保护层。在第一材料层和保护层中形成至少一个开口。在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。执行平面化处理以去除开口外部的第二材料层的部分。在平坦化处理期间，保护层的至少一部分不被去除。执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

4. 发明授权

US08163594B2 Semiconductor device comprising a carbon-based material for through hole vias 有权
标题翻译：包括用于通孔过孔的碳基材料的半导体器件
公开(公告)号：US08163594B2
公开(公告)日：2012-04-24
申请号：US12505098
申请日：2009-07-17
申请人： Robert Seidel , Frank Feustel , Ralf Richter
发明人： Robert Seidel , Frank Feustel , Ralf Richter
IPC分类号： H01L21/31
CPC分类号： H01L21/76898 , H01L23/53276 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/1305 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.
摘要翻译：在半导体器件中，可以基于含碳材料形成延伸穿过器件的衬底的通孔，从而与高温工艺相比具有优异的兼容性，同时与掺杂的半导体材料相比提供优异的电性能，类似。因此，在一些说明性实施例中，通孔过孔可以在用于形成关键电路元件的任何工艺步骤之前形成，从而基本上避免了通孔通孔结构与对应的半导体器件的器件级别的任何干扰。因此，可以实现高效率的三维集成方案。

5. 发明申请

US20090085173A1 SIDEWALL PROTECTION LAYER 审中-公开
标题翻译：防护层
公开(公告)号：US20090085173A1
公开(公告)日：2009-04-02
申请号：US12056356
申请日：2008-03-27
申请人： Juergen Boemmels , Frank Feustel , Ralf Richter
发明人： Juergen Boemmels , Frank Feustel , Ralf Richter
IPC分类号： H01L23/58 , H01L21/311 , H01L21/44
CPC分类号： H01L23/53295 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： The present disclosure generally relates to forming a metallization layer in a semiconductor device. In particular, this disclosure concerns the damascene inlay technique in low-k dielectric layers. Etching trenches and vias in low-k dielectric materials leads to uneven and porous sidewalls of the trenches and vias due to the porous nature of the low-k dielectric materials. Thus, smooth and dense sidewalls cannot be achieved, which is a prerequisite for an effective barrier layer, which prevents copper from being diffused into the low-k dielectric material. As a consequence, process tolerances are high and the reliability of the semiconductor device is reduced. The present disclosure overcomes these drawbacks by a surface treatment of the sidewalls of trenches and vias in order to densify the surface such that the following barrier layer may more effectively prevent copper from diffusing into the low-k or ultra high-k dielectric material.
摘要翻译：本公开一般涉及在半导体器件中形成金属化层。特别地，本公开涉及在低k电介质层中的镶嵌技术。由于低k介电材料的多孔性质，低k电介质材料中的蚀刻沟槽和通孔导致沟槽和通孔的不均匀和多孔的侧壁。因此，不能实现平滑和致密的侧壁，这是有效阻挡层的先决条件，其阻止铜扩散到低k电介质材料中。因此，工艺公差高，半导体器件的可靠性降低。本公开通过沟槽和通孔的侧壁的表面处理克服了这些缺点，以便使表面致密化，使得后续阻挡层可以更有效地防止铜扩散到低k或超高k电介质材料中。

6. 发明申请

US20080026492A1 METHOD OF REDUCING CONTAMINATION BY PROVIDING A REMOVABLE POLYMER PROTECTION FILM DURING MICROSTRUCTURE PROCESSING 有权
标题翻译：通过在微结构加工中提供可拆卸的聚合物保护膜来减少污染的方法
公开(公告)号：US20080026492A1
公开(公告)日：2008-01-31
申请号：US11695657
申请日：2007-04-03
申请人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/469 , H01L21/66
CPC分类号： H01L21/02074 , H01L21/0209 , H01L21/02096
摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
摘要翻译：通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

7. 发明授权

US07955962B2 Method of reducing contamination by providing a removable polymer protection film during microstructure processing 有权
标题翻译：通过在微结构处理期间提供可除去的聚合物保护膜来减少污染的方法
公开(公告)号：US07955962B2
公开(公告)日：2011-06-07
申请号：US11695657
申请日：2007-04-03
申请人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/20
CPC分类号： H01L21/02074 , H01L21/0209 , H01L21/02096
摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
摘要翻译：通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

8. 发明授权

US08216927B2 Method of reducing contamination by providing a removable polymer protection film during microstructure processing 有权
标题翻译：在微结构加工过程中提供可除去的聚合物保护膜来减少污染的方法
公开(公告)号：US08216927B2
公开(公告)日：2012-07-10
申请号：US13094144
申请日：2011-04-26
申请人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/20
CPC分类号： H01L21/02074 , H01L21/0209 , H01L21/02096
摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
摘要翻译：通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

9. 发明申请

US20110201135A1 Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing 有权
标题翻译：微结构加工过程中提供可拆卸聚合物保护膜减少污染的方法
公开(公告)号：US20110201135A1
公开(公告)日：2011-08-18
申请号：US13094144
申请日：2011-04-26
申请人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
发明人： Ralf Richter , Frank Feustel , Thomas Werner , Kai Frohberg
IPC分类号： H01L21/66
CPC分类号： H01L21/02074 , H01L21/0209 , H01L21/02096
摘要： By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process.
摘要翻译：通过在中间制造阶段提供保护层，可以实现相对于颗粒污染和表面腐蚀的增加的表面保护。在一些说明性实施例中，保护层可以在电测试过程中使用，其中相应的接触部分通过保护层接触，从而在相应的测量过程中显着地减少颗粒污染。

10. 发明授权

US08293641B2 Nano imprint technique with increased flexibility with respect to alignment and feature shaping 有权
标题翻译：纳米压印技术在对准和特征成形方面具有增加的灵活性
公开(公告)号：US08293641B2
公开(公告)日：2012-10-23
申请号：US13014771
申请日：2011-01-27
申请人： Robert Seidel , Carsten Peters , Frank Feustel
发明人： Robert Seidel , Carsten Peters , Frank Feustel
IPC分类号： H01L21/4763
CPC分类号： B81B7/0006 , B81C2201/0153 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/28114 , H01L21/76224 , H01L21/76229 , H01L21/76804 , H01L21/76807 , H01L21/76817 , H01L21/76838 , H01L21/76852 , H01L21/76885 , H01L2221/1021
摘要： By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.
摘要翻译：通过基于压印技术形成金属化结构，其中可以通常形成通孔和沟槽，由于根据常规工艺技术所要求的至少一个进一步对准过程，可以实现工艺复杂性的显着降低。此外，可以通过提供适当设计的压印模具来提高压印光刻的灵活性和效率，以便提供表现出增加的填充能力的通孔开口和沟槽，从而也提高了最终获得的金属化结构在可靠性，抗性电迁移等。

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