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    • 5. 发明申请
    • TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM
    • 非标准电路电路及相关机器可读介质的时序分析方法
    • US20150067623A1
    • 2015-03-05
    • US14450279
    • 2014-08-03
    • REALTEK SEMICONDUCTOR CORP.
    • Ying-Chieh ChenMei-Li YuTing-Hsiung WangYu-Lan LoShu-Yi Kao
    • G06F17/50
    • G06F17/5031G06F2217/84
    • A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register.
    • 一种应用于非标准单元电路的定时分析方法,包括:从电路识别至少第一寄存器和第二寄存器; 计算所述第一寄存器和所述第二寄存器之间的至少一个路径的至少一个路径延迟; 计算从第一时钟源到第一寄存器的第一寄存器时钟输入端的第一寄存器时钟延迟; 计算从第二时钟源到第二寄存器的第二寄存器时钟输入端的第二寄存器时钟延迟; 以及根据所述路径延迟,所述第一寄存器时钟延迟,所述第二寄存器时钟延迟以及所述第一寄存器的第一寄存器延迟确定是否针对所述第二寄存器发生定时违反。