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1. 发明授权

US4266270A Microprocessor having plural internal data buses 失效
标题翻译：具有多个内部数据总线的微处理器
公开(公告)号：US4266270A
公开(公告)日：1981-05-05
申请号：US939741
申请日：1978-09-05
申请人： R. Gary Daniels , Fuad H. Musa , William B. Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
发明人： R. Gary Daniels , Fuad H. Musa , William B. Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
IPC分类号： G06F7/00 , G06F9/30 , G06F15/78 , G06F1/00
CPC分类号： G06F15/7832
摘要： A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses. The provision plural internal data buses permits a greater number of transfers of digital information to occur within the microprocessor during each machine cycle. The result is more efficient microprocessor operation and higher throughput.
摘要翻译：微处理器包括具有第一部分（2,4）的内部地址总线，第一部分（2,4）具有承载低阶地址字节的多个导体，以及具有用于承载高位地址字节的多个导体的第二部分（10）。微处理器还包括多个寄存器，包括一个增量器（12,13），一个程序计数器（14,15），一个临时寄存器（16,17），堆栈指针（18,19），索引寄存器，21）和累加器（22,24），每个包括用于临时存储信息的一对8位寄存器。算术逻辑单元（28）对微处理器内的数字信息进行计算操作。微处理器包括一对内部数据总线（6,8），每个内部数据总线具有用于在微处理器内进行数字信息的多个导体。提供了用于将所选择的一个寄存器或其高阶或低阶部分耦合到第一和第二数据总线的装置。提供多个内部数据总线允许在每个机器周期期间在微处理器内发生更多数量的数字信息传送。结果是更高效的微处理器操作和更高的吞吐量。

2. 发明授权

US4409671A Data processor having single clock pin 失效
标题翻译：数据处理器具有单个时钟引脚
公开(公告)号：US4409671A
公开(公告)日：1983-10-11
申请号：US295912
申请日：1981-08-24
申请人： R. Gary Daniels , Thomas H. Bennett , Fuad H. Musa , Michael F. Wiles
发明人： R. Gary Daniels , Thomas H. Bennett , Fuad H. Musa , Michael F. Wiles
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/06
摘要： A microprocessor on a monolithic integrated circuit is provided having a single clock input pin for receiving a clock input signal. The clock input signal is used to gate address data onto the address bus and to enable a data input dynamic latch. In addition the input clock signal is used to generate two complementary non-overlapping clock signals used for synchronizing purposes within the microprocessor.
摘要翻译：提供了具有用于接收时钟输入信号的单个时钟输入引脚的单片集成电路上的微处理器。时钟输入信号用于将地址数据输入到地址总线上，并使数据输入动态锁存。此外，输入时钟信号用于产生用于微处理器内的同步目的的两个互补非重叠时钟信号。

3. 发明授权

US4203157A Carry anticipator circuit and method 失效
标题翻译：携带预测电路和方法
公开(公告)号：US4203157A
公开(公告)日：1980-05-13
申请号：US939724
申请日：1978-09-05
申请人： R. Gary Daniels , Fuad H. Musa , W. Bryant Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
发明人： R. Gary Daniels , Fuad H. Musa , W. Bryant Wilder, Jr. , Michael F. Wiles , Thomas H. Bennett
IPC分类号： G06F9/22 , G06F7/50 , G06F7/506 , G06F7/507 , G06F9/30 , G06F9/32 , G06F15/78
CPC分类号： G06F7/506 , G06F9/321 , G06F9/322 , G06F9/324
摘要： A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.
摘要翻译：公开了一种用于将8位操作数添加到16位操作数的电路和方法，使得数据处理器执行这种添加所需的机器周期数减少。 8位操作数和16位操作数的最低有效字节在8位加法器电路中相加在一起，以生成结果的最低有效字节。同时，16位操作数的最高有效字节存储在临时寄存器中，并且也被输入到递增/递减网络。在给定的延迟时间之后，加法器电路根据加法产生进位是否产生进位信号。 8位操作数的进位信号和符号位控制增量/减量网络的运行模式，并确定增量/减量网络或临时寄存器是否被选择以提供结果的最高有效字节。

4. 发明授权

US4330842A Valid memory address pin elimination 失效
标题翻译：有效的内存地址引脚消除
公开(公告)号：US4330842A
公开(公告)日：1982-05-18
申请号：US939723
申请日：1978-09-05
申请人： R. Gary Daniels , Thomas H. Bennett , Michael F. Wiles
发明人： R. Gary Daniels , Thomas H. Bennett , Michael F. Wiles
IPC分类号： G06F1/22 , G06F13/42 , G06F3/00 , G06F13/00
CPC分类号： G06F1/22 , G06F13/4243
摘要： A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic "1's" are generated on the address output bus.
摘要翻译：提供了单个单片集成电路芯片上的数字数据处理器，其使用少一个引脚。通过在处理器内部使用有效的存储器地址信号到从地址到地址输出线的门信息来实现引脚的消除。每当地址总线上不存在地址时，地址输出总线上都会产生逻辑“1”。

5. 发明授权

US4030079A Processor including incrementor and program register structure 失效
标题翻译：处理器包括增量器和程序寄存器结构
公开(公告)号：US4030079A
公开(公告)日：1977-06-14
申请号：US719889
申请日：1976-09-02
申请人： Thomas H. Bennett , Earl F. Carlow , Anthony E. Kouvoussis , Rodney H. Orgill , Charles Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Anthony E. Kouvoussis , Rodney H. Orgill , Charles Peddle , Michael F. Wiles
IPC分类号： G06F9/30 , G06F9/32 , G06F9/355 , G06F15/78 , G06F7/50
CPC分类号： G06F9/342 , G06F15/7832 , G06F9/32 , G06F9/321 , G06F9/3557
摘要： A processor including a first bus, a second bus, and a control circuit for producing control signals includes a counter having a plurality of inputs and outputs responsive to the control circuit and coupled between the first and second buses for incrementing digital information present at the inputs of the counter. The processor includes a first coupling circuit responsive to the control circuit for coupling the counter inputs to the first bus to effect transferring digital information from the first bus to the counter inputs. A second coupling circuit couples the counter inputs to the second bus to transfer digital information from the second bus to the counter inputs in response to the control circuit. A third coupling circuit couples the counter outputs to the second bus to transfer digital information from the counter output to the second bus. When the second and third coupling circuits are both simultaneously activated in response to the control circuit, digital information present at the counter inputs is effectively latched and temporarily stored in the circuit formed by the counter and the second and third coupling circuits. The processor also includes a program register coupled between the first and second buses for temporarily storing digital information received from the counter means by means of a fourth coupling circuit, which operatively couples the outputs of the counter to inputs of the program register to effect transferring digital information from the counter outputs to the program register inputs in response to the control circuit. Fifth and sixth coupling circuits operatively couple the program register outputs to the first or second bus in response to the control circuit to effect transferring digital information from the program register to the first or second buses, respectively.
摘要翻译：包括第一总线，第二总线和用于产生控制信号的控制电路的处理器包括响应于控制电路并且耦合在第一和第二总线之间的多个输入和输出的计数器，用于增加存在于输入端的数字信息的柜台处理器包括响应于控制电路的第一耦合电路，用于将计数器输入耦合到第一总线，以实现将数字信息从第一总线传送到计数器输入。第二耦合电路将计数器输入耦合到第二总线，以响应于控制电路将数字信息从第二总线传送到计数器输入。第三耦合电路将计数器输出耦合到第二总线，以将数字信息从计数器输出传送到第二总线。当响应于控制电路同时激活第二和第三耦合电路时，存在于计数器输入端的数字信息被有效地锁存并临时存储在由计数器和第二和第三耦合电路形成的电路中。处理器还包括耦合在第一和第二总线之间的程序寄存器，用于通过第四耦合电路临时存储从计数器装置接收的数字信息，该第四耦合电路可操作地将计数器的输出耦合到程序寄存器的输入以实现数字响应于控制电路从计数器输出到程序寄存器输入的信息。第五和第六耦合电路响应于控制电路将编程寄存器输出可操作地耦合到第一或第二总线，以分别将数字信息从程序寄存器传送到第一或第二总线。

6. 发明授权

US4020472A Master slave registers for interface adaptor 失效
标题翻译：接口适配器的主从寄存器
公开(公告)号：US4020472A
公开(公告)日：1977-04-26
申请号：US614114
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/00
CPC分类号： G06F13/38 , G06F13/24
摘要： An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system. The interface adaptor includes a plurality of registers, including a control register and a data register, coupled to the input register by means of an internal input bus. Each of the plurality of registers includes flip-flops which are coupled as slave flip-flops to corresponding flip-flops of the input register. The corresponding flip-flops of the input register function as master flip-flops. The interface adaptor also includes register selection logic circuitry for selecting one of the plurality of registers by electrically coupling its slave flip-flop to the corresponding master flip-flops of the input register.
摘要翻译：适用于微处理器系统的接口适配器包括耦合到微处理器系统的双向数据总线的输入寄存器。接口适配器包括多个寄存器，包括通过内部输入总线耦合到输入寄存器的控制寄存器和数据寄存器。多个寄存器中的每一个包括作为从触发器耦合到输入寄存器的相应触发器的触发器。输入寄存器的相应触发器用作主触发器。接口适配器还包括寄存器选择逻辑电路，用于通过将其从触发器电耦合到输入寄存器的相应主触发器来选择多个寄存器中的一个。

7. 发明授权

US4010448A Interrupt circuitry for microprocessor chip 失效
标题翻译：中断电路用于微处理器芯片
公开(公告)号：US4010448A
公开(公告)日：1977-03-01
申请号：US519140
申请日：1974-10-30
申请人： Thomas H. Bennett , Earl F. Carlow , Anthony E. Kouvoussis , Rodney H. Orgill , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Anthony E. Kouvoussis , Rodney H. Orgill , Michael F. Wiles
IPC分类号： G06F13/24 , G06F15/78 , G06F9/18
CPC分类号： G06F15/7832 , G06F13/24
摘要： Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

8. 发明授权

US4263650A Digital data processing system with interface adaptor having programmable, monitorable control register therein 失效
标题翻译：具有接口适配器的数字数据处理系统，其中具有可编程的，可监控的控制寄存器
公开(公告)号：US4263650A
公开(公告)日：1981-04-21
申请号：US7752
申请日：1979-01-30
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/04 , G06F9/00 , G06F13/00
CPC分类号： G06F13/24 , G06F13/38
摘要： A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.
摘要翻译：一种数字系统，包括多个金属氧化物半导体（MOS）芯片随机存取存储器（RAM），只读存储器（ROM）和耦合到公共双向数据总线的外围接口适配器，该公共双向数据总线耦合到微处理器单元（MPU）。每个外设接口适配器都包含一个可在程序控制下加载的控制寄存器。控制寄存器的内容控制接口适配器内几个寄存器的选择。控制寄存器还控制外围接口适配器的其他功能，包括确定接口适配器外围缓冲区中数据移动的方向。每个接口适配器的控制寄存器的内容可由微处理器单元监视。

9. 发明授权

US4218740A Interface adaptor architecture 失效
标题翻译：接口适配器架构
公开(公告)号：US4218740A
公开(公告)日：1980-08-19
申请号：US757120
申请日：1977-01-05
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , William D. Mensch, Jr. , Charles I. Peddle , Gene A. Schriber , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , William D. Mensch, Jr. , Charles I. Peddle , Gene A. Schriber , Michael F. Wiles
IPC分类号： G06F13/24 , G06F13/38 , G06F3/00
CPC分类号： G06F13/38 , G06F13/24
摘要： A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA.The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.
摘要翻译：用于数据处理系统的外围接口适配器（PIA）电路包含存储器元件或控制寄存器，允许在程序控制下对PIA的逻辑功能进行修改。外围接口适配器包括耦合到系统数据总线的多个系统数据总线缓冲电路，并且还包括耦合到双向外围数据总线的外围接口缓冲电路。外围数据总线中数据流的方向由数据方向寄存器控制。来自系统数据总线缓冲器的数据被输入到输入寄存器中，并且从那里传送到耦合到控制寄存器，数据方向寄存器和数据寄存器的输入总线。来自外围数据总线，数据方向寄存器和控制寄存器的数据通过输出总线传送到系统数据总线缓冲器。控制信号由选择，读/写控制和寄存器选择逻辑产生，该逻辑在耦合到输入寄存器，数据寄存器，控制寄存器和数据方向寄存器的控制总线上提供信号，以控制各种总线之间的数据传输，寄存器和缓冲电路。

10. 发明授权

US4086627A Interrupt system for microprocessor system 失效
标题翻译：微处理器系统中断系统
公开(公告)号：US4086627A
公开(公告)日：1978-04-25
申请号：US614110
申请日：1975-09-17
申请人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
发明人： Thomas H. Bennett , Earl F. Carlow , Edward C. Hepworth , Wilbur L. Mathys , William D. Mensch, Jr. , Rodney H. Orgill , Charles I. Peddle , Michael F. Wiles
IPC分类号： G06F9/30 , G06F13/24 , G06F13/38 , G06F15/78 , H04L25/30 , G06F9/18
CPC分类号： G06F13/24 , G06F13/38
摘要： A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.
摘要翻译：微处理器系统包括微处理器，存储器和全部耦合到数据总线的接口适配器。接口适配器耦合在数据总线和外围设备之间，如电传打印机。第一个中断导体连接到外围设备，并中断接口适配器中的逻辑电路。第二个中断导体连接到微处理器和中断逻辑电路。中断逻辑电路也通过数据总线耦合到微处理器并可询问。中断逻辑电路存储来自数据总线的中断控制信息，并响应于存储的中断控制信息和由外围设备在第一中断导体上产生的中断信号，在第二中断导体上产生第二中断信号。中断逻辑电路还存储指示第一中断信号的出现的状态信息，并通过数据总线影响该状态的询问。

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