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1. 发明授权

US06271127B1 Method for dual damascene process using electron beam and ion implantation cure methods for low dielectric constant materials 有权
标题翻译：使用电子束的双镶嵌工艺和低介电常数材料的离子注入固化方法
公开(公告)号：US06271127B1
公开(公告)日：2001-08-07
申请号：US09329569
申请日：1999-06-10
申请人： Qizhi Liu , David Feiler , Bin Zhao , Maureen R. Brongo
发明人： Qizhi Liu , David Feiler , Bin Zhao , Maureen R. Brongo
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/7681 , H01L21/76811 , H01L21/76825 , Y10S438/949
摘要： Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.
摘要翻译：用于半导体工件的双镶嵌金属化的方法，其使用在绝缘体中产生蚀刻停止的工艺，从而消除了沉积蚀刻停止层的需要。使用电子束曝光来固化绝缘体或具有低介电常数的材料。将电子束应用于低介电常数材料将低介电常数材料的最上层转化为蚀刻停止层，同时快速热加热固化低介电常数材料的其余部分。在低介电常数材料中形成蚀刻停止层也可以通过使用离子注入固化低介电常数材料来实现。

2. 发明授权

US07060557B1 Fabrication of high-density capacitors for mixed signal/RF circuits 有权
标题翻译：用于混合信号/ RF电路的高密度电容器的制造
公开(公告)号：US07060557B1
公开(公告)日：2006-06-13
申请号：US10190297
申请日：2002-07-05
申请人： Bin Zhao , Qizhi Liu , Maureen R. Brongo
发明人： Bin Zhao , Qizhi Liu , Maureen R. Brongo
IPC分类号： H01L21/8242
CPC分类号： H01L28/91
摘要： A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The underlying cap dielectric layer may be modified in a way that increases its dielectric constant as a result of simultaneously be heated by a heat source and impinged with and energy beam. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.
摘要翻译：公开了一种在半导体衬底上制造电容器的方法。该方法可以包括同时形成至少一个通孔和至少一个上电容器板开口，该第一电介质层具有沉积在具有导电区域内的第一导电材料的第一材料区域上的底层盖电介质层，并且形成在通过。底层盖电介质层可以以增加其介电常数的方式进行修改，这是由于同时被热源加热并与其碰撞而产生的能量束。该方法还可以包括用第二导电材料填充通孔，沟槽和上电容器板开口，得到集成电路结构，并采用CMP从集成电路结构中去除任何多余的第二导电材料。

3. 发明授权

US06627539B1 Method of forming dual-damascene interconnect structures employing low-k dielectric materials 有权
标题翻译：使用低k电介质材料形成双镶嵌互连结构的方法
公开(公告)号：US06627539B1
公开(公告)日：2003-09-30
申请号：US09149910
申请日：1998-09-09
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L2144
CPC分类号： H01L23/5329 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： Interconnects in sub-micron and sub-half-micron integrated circuit devices are fabricated using a dual damascene process incorporating a low-k dielectric. A dual-damascene structure can be implemented without the necessity of building a single damascene base, and without CMP of the low-k dielectric. This structure simplifies the manufacturing process, reduces cost, and effectively reduces intra-level and inter-level capacitance, resistivity, and noise related to substrate coupling. In accordance with a further aspect of the present invention, a modified silicon oxide material such as silsesquioxane is used for the low-k dielectric in conjunction with silicon dioxide cap layers, allowing an improved process window and simplifying the etching process.
摘要翻译：使用包含低k电介质的双镶嵌工艺制造亚微米和亚半微米集成电路器件中的互连。可以实现双镶嵌结构，而不需要构建单个镶嵌基底，并且不需要低k电介质的CMP。该结构简化了制造工艺，降低了成本，并且有效地降低了与衬底耦合有关的电平，电平和电平以及噪声。根据本发明的另一方面，与二氧化硅盖层结合使用改性氧化硅材料如倍半硅氧烷用于低k电介质，允许改进的工艺窗口并简化蚀刻工艺。

4. 发明授权

US06187672B1 Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing 有权
标题翻译：与半导体集成电路制造的低介电常数绝缘体互连
公开(公告)号：US06187672B1
公开(公告)日：2001-02-13
申请号：US09158337
申请日：1998-09-22
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76819 , H01L21/76834
摘要： A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.
摘要翻译：提供了一种用于在半导体本体上形成改进的互连结构的方法。第一金属层沉积在半导体本体上。具有高度的牺牲层沉积在第一金属层上。牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。然后沉积低k材料以填充金属线之间的间隙并覆盖牺牲层。然后将低k材料去除到牺牲层的高度内的水平。然后去除牺牲层。保护层沉积在金属线和低k材料的顶部。介电层沉积在保护层上。保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂和清洁通孔。然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

5. 发明授权

US06787911B1 Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing 有权
标题翻译：与半导体集成电路制造的低介电常数绝缘体互连
公开(公告)号：US06787911B1
公开(公告)日：2004-09-07
申请号：US09317536
申请日：1999-05-24
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L2348
CPC分类号： H01L21/76802 , H01L21/76801 , H01L21/76819 , H01L21/76834
摘要： A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A look material is then deposited to fill the gaps bet n metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A prove layer is deposited on top of the metal lines and the look material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photoresist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.
摘要翻译：提供了一种用于在半导体本体上形成改进的互连结构的方法。第一金属层沉积在半导体本体上。具有高度的牺牲层沉积在第一金属层上。牺牲层和金属层被图案化以形成分离的金属线，牺牲层保留在所述金属线上。然后沉积外观材料以填充金属线上的间隙并覆盖牺牲层。然后将低k材料去除到牺牲层的高度内的水平。然后去除牺牲层。证明层沉积在金属线和外观材料的顶部。介电层沉积在保护层上。保护层保护低k材料免受后续工艺步骤所用化学品的侵蚀，以蚀刻电介质层中的通孔，剥离光致抗蚀剂，并清洁通孔。然后选择性地蚀刻保护层以使通孔塞和金属线之间的接触。

6. 发明授权

US06984577B1 Damascene interconnect structure and fabrication method having air gaps between metal lines and metal layers 有权
标题翻译：具有金属线和金属层之间气隙的镶嵌互连结构和制造方法
公开(公告)号：US06984577B1
公开(公告)日：2006-01-10
申请号：US09665422
申请日：2000-09-20
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76802 , H01L21/76807 , H01L21/7681 , H01L21/76832 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene interconnect that reduces interconnect intra-layer capacitance and/or inter-layer capacitance is provided. The damascene interconnect structure has air gaps between metal lines and/or metal layers. The interconnect structure is fabricated to a via level through a processing step prior to forming contact vias, then one or more air gaps are formed into the damascene structure so that the air gaps are positioned between selected metal lines. A sealing layer is then deposited over the damascene structure to seal the air gaps.
摘要翻译：提供了减少互连层内电容和/或层间电容的镶嵌互连。镶嵌互连结构在金属线和/或金属层之间具有气隙。在形成接触通孔之前，通过处理步骤将互连结构制成通孔级，然后将一个或多个气隙形成到镶嵌结构中，使得气隙位于选定的金属线之间。然后将密封层沉积在镶嵌结构上以密封气隙。

7. 发明授权

US06245663B1 IC interconnect structures and methods for making same 有权
标题翻译： IC互连结构及其制造方法
公开(公告)号：US06245663B1
公开(公告)日：2001-06-12
申请号：US09163967
申请日：1998-09-30
申请人： Bin Zhao , Maureen R. Brongo
发明人： Bin Zhao , Maureen R. Brongo
IPC分类号： H01L214763
CPC分类号： H01L21/76834 , H01L21/76807 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. a dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.
摘要翻译：公开了使用单个镶嵌工艺制造的亚微米级和次级半微米集成电路器件中的高级互连的方法和结构。在先前的金属化层（例如，导电插头）的CMP处理之前而不是之前沉积介电蚀刻停止层（例如，氮化硅）。该方案有效地消除了CMP腐蚀对蚀刻停止层的影响，因此允许使用极薄的蚀刻停止。此外，可以获得沟槽蚀刻的高蚀刻选择性，并且从互连金属下方去除所有蚀刻停止材料，从而减少寄生效应。图案化的介电层用作代替标准覆盖氮化硅层的金属盖，从而防止与被捕获的湿气和气体相关联的起泡和气泡的形成，并减少互连电容。

8. 发明授权

US07109125B1 Selective fabrication of high capacitance density areas in a low dielectric constant material 有权
标题翻译：在低介电常数材料中选择性地制造高电容密度区域
公开(公告)号：US07109125B1
公开(公告)日：2006-09-19
申请号：US10995762
申请日：2004-11-22
申请人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
发明人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
IPC分类号： H01L21/302 , H01L21/461 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/86 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered, for example with photoresist, while a second area of the dielectric layer is exposed to a dielectric conversion source such as E-beams, I-beams, oxygen plasma, or an appropriate chemical. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of capacitor trenches are etched in the second area of the dielectric. The capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area. In another embodiment, the exposure to the dielectric conversion source is not performed until after the chemical mechanical polish has been performed. In yet another embodiment, a blanket layer of metal, such as aluminum, is first deposited. The blanket layer of metal is then etched to form metal lines. Then a gap fill dielectric is utilized to fill the gaps between the remaining metal lines. A first area of the gap fill dielectric is then covered and a second area of the gap fill dielectric is exposed to a dielectric conversion source. After exposure to the dielectric conversion source, the dielectric constant of the gap fill dielectric in the second area increases. The metal lines in the second area can then be used as capacitor electrodes of a high density capacitor.
摘要翻译：公开了用于选择性地制造低介电常数材料和相关结构中的高电容密度区域的方法。在一个实施例中，电介质层的第一区域例如被光致抗蚀剂覆盖，而介电层的第二区域暴露于电介质转换源（例如电子束，I型波束，氧等离子体）或适当的化学品。曝光导致第二区域中介电层的介电常数增加。在电介质的第二区域中蚀刻多个电容器沟槽。然后用适当的金属（例如铜）填充电容器沟槽，并进行化学机械抛光。其中电容器沟槽被蚀刻和填充的第二区域相对于第一区域具有较高的电容密度。在另一个实施例中，直到进行化学机械抛光之后，不进行介电转换源的曝光。在又一实施例中，首先沉积诸如铝的金属覆盖层。然后蚀刻金属覆盖层以形成金属线。然后使用间隙填充电介质来填充剩余金属线之间的间隙。然后覆盖间隙填充电介质的第一区域，并且间隙填充电介质的第二区域暴露于电介质转换源。在暴露于电介质转换源之后，第二区域中间隙填充电介质的介电常数增加。然后可以将第二区域中的金属线用作高密度电容器的电容器电极。

9. 发明授权

US07049246B1 Method for selective fabrication of high capacitance density areas in a low dielectric constant material 有权
标题翻译：用于在低介电常数材料中选择性地制造高电容密度区域的方法
公开(公告)号：US07049246B1
公开(公告)日：2006-05-23
申请号：US09575055
申请日：2000-05-19
申请人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
发明人： Q. Z. Liu , David Feiler , Bin Zhao , Phil N. Sherman , Maureen Brongo
IPC分类号： H01L21/302 , H01L21/461 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/86 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Method for selective fabrication of high capacitance density areas in a low dielectric constant material and related structure are disclosed. In one embodiment, a first area of a dielectric layer is covered while a second area of the dielectric layer is exposed to a dielectric conversion source. The exposure causes the dielectric constant of the dielectric layer in the second area to increase. A number of interconnect trenches are etched in the first area of the dielectric and a number of capacitor trenches are etched in the second area of the dielectric. The interconnect trenches and the capacitor trenches are then filled with an appropriate metal, such as copper, and a chemical mechanical polish is performed. The second area in which the capacitor trenches have been etched and filled has a higher capacitance density relative to the first area.
摘要翻译：公开了用于选择性地制造低介电常数材料和相关结构中的高电容密度区域的方法。在一个实施例中，电介质层的第一区域被覆盖，同时介电层的第二区域暴露于电介质转换源。曝光导致第二区域中介电层的介电常数增加。在电介质的第一区域中蚀刻多个互连沟槽，并且在电介质的第二区域中蚀刻多个电容器沟槽。然后用适当的金属（例如铜）填充互连沟槽和电容器沟槽，并进行化学机械抛光。其中电容器沟槽被蚀刻和填充的第二区域相对于第一区域具有较高的电容密度。

10. 发明授权

US10212958B2 Method for producing stabilized whole wheat flour 有权
公开(公告)号：US10212958B2
公开(公告)日：2019-02-26
申请号：US14111679
申请日：2012-04-13
申请人： Bin Zhao , Ning Zhou , Timothy S. Hansen , Michael A. Duffin , Domenico R. Cassone , Diane L. Gannon , Lynn C. Haynes , James M. Manns , Jeanny E. Zimeri , Peter Worfolk , Anthony Pracek
发明人： Bin Zhao , Ning Zhou , Timothy S. Hansen , Michael A. Duffin , Domenico R. Cassone , Diane L. Gannon , Lynn C. Haynes , James M. Manns , Jeanny E. Zimeri , Peter Worfolk , Anthony Pracek
IPC分类号： A23L1/211 , A23L7/10 , A21D2/14 , A21D2/36 , A21D2/38 , A21D6/00 , A21D13/02 , B02B1/08
摘要： A stabilized flour, such as stabilized whole grain wheat flour, exhibiting unexpectedly superior extended shelf life and superior biscuit baking functionality, may be produced with or without heating to inhibit lipase by subjecting whole grains or a bran and germ fraction or component to treatment with a lipase inhibitor, such as an acid or green tea extract. Treatment with the lipase inhibitor may be performed during tempering of the whole grains or berries or during hydration of the bran and germ fraction or component.

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