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1. 发明申请

US20080280404A1 RESIDUE FREE PATTERNED LAYER FORMATION METHOD APPLICABLE TO CMOS STRUCTURES 有权
标题翻译：适用于CMOS结构的残留层形成方法
公开(公告)号：US20080280404A1
公开(公告)日：2008-11-13
申请号：US11746759
申请日：2007-05-10
申请人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
发明人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28 , H01L21/02 , H01L21/311
CPC分类号： H01L29/045 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823842 , H01L21/823857 , H01L21/84
摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different NFET and pFET gate electrode materials.
摘要翻译：形成微电子结构的方法使用位于目标层上的掩模层。可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的NFET和pFET栅电极材料。

2. 发明授权

US07863124B2 Residue free patterned layer formation method applicable to CMOS structures 有权
标题翻译：无残留图案层形成方法适用于CMOS结构
公开(公告)号：US07863124B2
公开(公告)日：2011-01-04
申请号：US11746759
申请日：2007-05-10
申请人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
发明人： Michael Chudzik , Bruce B. Doris , William K. Henson , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/045 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/31138 , H01L21/32137 , H01L21/32139 , H01L21/823842 , H01L21/823857 , H01L21/84
摘要： A method for forming a microelectronic structure uses a mask layer located over a target layer. The target layer may be etched while using the mask layer as an etch mask to form an end tapered target layer from the target layer. An additional target layer may be formed over the end tapered target layer and masked with an additional mask layer. The additional target layer may be etched to form a patterned additional target layer separated from the end tapered target layer and absent an additional target layer residue adjacent the end tapered target layer. The method is useful for fabricating CMOS structures including nFET and pFET gate electrodes comprising different nFET and pFET gate electrode materials.
摘要翻译：形成微电子结构的方法使用位于目标层上的掩模层。可以使用掩模层作为蚀刻掩模来蚀刻目标层，以从目标层形成端部锥形目标层。可以在端部锥形目标层上形成另外的目标层，并用附加掩模层掩模。可以蚀刻附加目标层以形成与端部锥形目标层分离的图案化附加目标层，并且不存在与端部锥形目标层相邻的附加靶层残余物。该方法对于制造包括nFET和pFET栅电极的CMOS结构是有用的，其包括不同的nFET和pFET栅电极材料。

3. 发明申请

US20080224238A1 ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK 有权
标题翻译：先进的高k栅格堆叠图案和结构包含一个图案高k门板堆叠
公开(公告)号：US20080224238A1
公开(公告)日：2008-09-18
申请号：US11685558
申请日：2007-03-13
申请人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
发明人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
IPC分类号： H01L29/76 , H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/31144 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
摘要翻译：提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

4. 发明授权

US07435652B1 Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介质金属栅极MOSFET的集成方案
公开(公告)号：US07435652B1
公开(公告)日：2008-10-14
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

5. 发明授权

US07820552B2 Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack 有权
标题翻译：先进的高k栅极堆叠图案和包含图案化的高k栅极堆叠的结构
公开(公告)号：US07820552B2
公开(公告)日：2010-10-26
申请号：US11685558
申请日：2007-03-13
申请人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
发明人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
IPC分类号： H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/31144 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
摘要翻译：提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

6. 发明申请

US20080242070A1 INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET 有权
标题翻译：用于制造多晶硅栅极MOSFET和高K介电金属栅极MOSFET的集成方案
公开(公告)号：US20080242070A1
公开(公告)日：2008-10-02
申请号：US11694104
申请日：2007-03-30
申请人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Tze-chiang Chen , Bruce B. Doris , Rangarajan Jagannathan , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28194 , H01L21/82345 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517
摘要： Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks.
摘要翻译：公开了用于制造双栅极半导体结构的多重集成方案。通过采用新颖的集成方案，尽管栅极堆叠的组成差异以及蚀刻速率的差异，但是在同一半导体衬底上形成多晶硅栅极MOSFET和高k介质金属栅极MOSFET。对于一种类型的栅电极使用薄多晶硅层，并且在这些集成方案中使用含硅层用于其他类型的栅电极，以平衡不同的蚀刻速率并且能够蚀刻两个不同的栅极堆叠。

7. 发明授权

US07820555B2 Method of patterning multilayer metal gate structures for CMOS devices 有权
标题翻译： CMOS器件的多层金属栅极结构图形化方法
公开(公告)号：US07820555B2
公开(公告)日：2010-10-26
申请号：US11870577
申请日：2007-10-11
申请人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/823828 , H01L29/4966 , H01L29/51
摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层门堆在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

8. 发明申请

US20090098737A1 METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的多层金属栅结构的方法
公开(公告)号：US20090098737A1
公开(公告)日：2009-04-16
申请号：US11870577
申请日：2007-10-11
申请人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
发明人： Bruce B. Doris , Richard S. Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/461
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/823828 , H01L29/4966 , H01L29/51
摘要： A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.
摘要翻译：形成用于互补金属氧化物半导体（CMOS）器件的图案化多层金属栅极结构的方法包括执行第一蚀刻工艺以去除包括在栅极堆叠内的多晶硅层的暴露部分，形成在也包括在栅极堆叠内的金属层上的多晶硅层门堆在第一蚀刻工艺之后氧化暴露的金属层的顶部部分，以便产生相对于多晶硅层具有蚀刻选择性的金属氧化物层; 通过物理离子轰击的组合除去金属氧化物层，并向其中引入各向同性化学成分，以防止多晶硅层底角的氧化物质; 以及执行第二蚀刻工艺以去除所述金属层的暴露部分。

9. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

10. 发明申请

US20090179283A1 METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES 有权
标题翻译：用于CMOS器件的金属栅极堆叠和半导体栅极堆叠
公开(公告)号：US20090179283A1
公开(公告)日：2009-07-16
申请号：US11954918
申请日：2007-12-12
申请人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
发明人： Charlotte D. Adams , Bruce B. Doris , Philip Fisher , William K. Henson , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/78
摘要： A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.
摘要翻译：包括基于氧化硅的栅极电介质和掺杂的半导体材料的半导体栅极堆叠形成在半导体衬底上。还在半导体衬底上形成包括高k栅极电介质和金属栅极部分的高k材料金属栅电极。在半导体栅极堆叠和高k材料金属栅极堆叠的侧壁上形成氧气不可渗透的电介质间隔物。除去半导体栅极堆叠上的不透氧电介质间隔物，同时保留高k材料金属栅电极上的不透氧电介质间隔物。在半导体栅极叠层上形成一个低k电介质隔离层，为采用半导体栅极堆叠的器件提供了低寄生电容。

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