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1. 发明申请

US20130078761A1 METHOD FOR MANUFACTURING A FLEXIBLE TRANSPARENT 1T1R STORAGE UNIT BASED ON A COMPLETELY LOW-TEMPERATURE PROCESS 审中-公开
标题翻译：基于完全低温过程制造柔性透明1T1R储存单元的方法
公开(公告)号：US20130078761A1
公开(公告)日：2013-03-28
申请号：US13528462
申请日：2012-06-20
申请人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/336
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1616
摘要： The present invention belongs to the technical field of low temperature atomic layer deposition technology, and specifically relates to a method for manufacturing a flexible transparent 1T1R storage unit. In the present invention, a fully transparent 1T1R storage unit is developed on a flexible substrate through a completely low-temperature process, including an oxide layer dielectric, a transparent electrode and a transparent substrate which are deposited together through a low-temperature process, thus realizing a fully transparent device capable of achieving the functions of nontransparent devices. The present invention can be applied to the manufacturing of flexible low-temperature storage units in the future, as well as changing the packaging and existing modes of devices, which will make foldable and bendable portable storage units possible.
摘要翻译：本发明属于低温原子层沉积技术的技术领域，具体涉及柔性透明1T1R存储单元的制造方法。在本发明中，完全透明的1T1R存储单元通过完全低温处理在柔性基板上开发，包括通过低温工艺沉积在一起的氧化物层电介质，透明电极和透明衬底，因此实现能够实现非透明设备功能的完全透明的设备。本发明可以应用于将来的柔性低温存储单元的制造，以及改变装置的现有模式，这使得可折叠和可弯曲的便携式存储装置成为可能。

2. 发明授权

US08455372B2 Method for cleaning and passivating gallium arsenide surface autologous oxide and depositing AL203 dielectric 有权
标题翻译：用于清除和钝化砷化镓表面自氧化物和沉积AL203电介质的方法
公开(公告)号：US08455372B2
公开(公告)日：2013-06-04
申请号：US13528509
申请日：2012-06-20
申请人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/31 , H01L21/00 , C30B28/06
CPC分类号： H01L21/0228 , H01L21/02052 , H01L21/02178 , H01L21/02301 , H01L21/02312 , H01L21/306
摘要： The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.
摘要翻译：本发明属于半导体材料的技术领域，具体涉及一种清洗和钝化砷化镓（GaAs）表面自氧化物并沉积Al2O3电介质的方法。该方法包括：使用新型硫钝化剂与GaAs表面的自氧化物反应，对其进行清洗，并产生钝化的硫化物膜，使GaAs与外界环境分离，从而防止GaAs再次氧化; 通过Al2O3 ALD的反应物三甲基铝（TMA）与GaAs表面的预处理反应，进一步清洗GaAs表面上的残余物，如自生氧化物和硫化物，然后通过ALD作为栅极电介质沉积高质量的Al2O3电介质其将GaAs与外部环境完全分离。本发明具有简单的工艺和良好的效果，并且可以为制造GaAs器件提供前提条件。

3. 发明申请

US20130078819A1 METHOD FOR CLEANING & PASSIVATING GALLIUM ARSENIDE SURFACE AUTOLOGOUS OXIDE AND DEPOSITING AL2O3 DIELECTRIC 有权
标题翻译：用于清洁和钝化铝酸盐表面氧化物和沉积Al2O3电介质的方法
公开(公告)号：US20130078819A1
公开(公告)日：2013-03-28
申请号：US13528509
申请日：2012-06-20
申请人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Runchen Fang , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/316
CPC分类号： H01L21/0228 , H01L21/02052 , H01L21/02178 , H01L21/02301 , H01L21/02312 , H01L21/306
摘要： The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning & passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.
摘要翻译：本发明属于半导体材料的技术领域，具体涉及一种清洗和钝化砷化镓（GaAs）表面自氧化物并沉积Al2O3电介质的方法。该方法包括：使用新型硫钝化剂与GaAs表面的自氧化物反应，对其进行清洗，并产生钝化的硫化物膜，使GaAs与外界环境分离，从而防止GaAs再次氧化; 通过Al2O3 ALD的反应物三甲基铝（TMA）与GaAs表面的预处理反应，进一步清洗GaAs表面上的残余物，如自生氧化物和硫化物，然后通过ALD作为栅极电介质沉积高质量的Al2O3电介质其将GaAs与外部环境完全分离。本发明具有简单的工艺和良好的效果，并且可以为制造GaAs器件提供前提条件。

4. 发明申请

US20130078797A1 METHOD FOR MANUFACTURING A COPPER-DIFFUSION BARRIER LAYER USED IN NANO INTEGRATED CIRCUIT 审中-公开
标题翻译：在纳米集成电路中使用的铜扩散阻挡层的制造方法
公开(公告)号：US20130078797A1
公开(公告)日：2013-03-28
申请号：US13528363
申请日：2012-06-20
申请人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/28562 , C23C16/18 , C23C16/45534 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for manufacturing a copper-diffusion barrier layer. In the present invention, a proper reaction precursor has been selected and the atomic layer deposition (ALD) technology has been adopted to develop Co or Ru on a TaN layer to obtain a diffusion barrier layer used in the interconnection for process nodes no more than 32 nm, which overcomes the insufficiency of the PVD deposition Ta/TaN double-layer structure as the copper-diffusion barrier layer in step coverage and conformity, and also effectively solves various serious problems in the Cu/low-k dual damascene process, such as the generation of voids in grooves and through-holes, and electromigration stability.
摘要翻译：本发明属于集成半导体电路的技术领域，涉及铜扩散阻挡层的制造方法。在本发明中，已经选择了适当的反应前体，并且已经采用原子层沉积（ALD）技术来在TaN层上形成Co或Ru，以获得在不超过32个工艺节点的互连中使用的扩散阻挡层 nm，克服了PVD沉积Ta / TaN双层结构作为铜扩散阻挡层在步骤覆盖和一致性方面的不足，并且有效地解决了Cu / low-k双镶嵌工艺中的各种严重问题，如凹槽和通孔中的空隙的产生以及电迁移稳定性。

5. 发明授权

US09153500B2 Method for improving the electromigration resistance in the copper interconnection process 有权
标题翻译：提高铜互连过程中的电迁移阻力的方法
公开(公告)号：US09153500B2
公开(公告)日：2015-10-06
申请号：US13528474
申请日：2012-06-20
申请人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/44 , H01L21/8238 , H01L23/532 , H01L21/768
CPC分类号： H01L21/823871 , H01L21/76805 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76865 , H01L21/76867 , H01L21/76895 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi3, CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.
摘要翻译：本发明属于集成半导体电路的技术领域，涉及在不超过32nm的工艺中使用的方法来提高Cu互连的电迁移率。铜互连上的涂层如CuSi3，CuGe和CuSiN可以通过自动配准来制备，并且通过使用新的不透水层材料，可以大大提高Cu互连的电迁移电阻，并且可以保持高导电性，这为不超过32nm的工艺节点的互连工艺提供了理想的解决方案。

6. 发明申请

US20130078798A1 METHOD FOR IMPROVING THE ELECTROMIGRATION RESISTANCE IN THE COPPER INTERCONNECTION PROCESS 有权
标题翻译：提高铜相互连接过程中电阻率的方法
公开(公告)号：US20130078798A1
公开(公告)日：2013-03-28
申请号：US13528474
申请日：2012-06-20
申请人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
发明人： Qingqing Sun , Lin Chen , Wen Yang , Pengfei Wang , Wei Zhang
IPC分类号： H01L21/768
CPC分类号： H01L21/823871 , H01L21/76805 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76856 , H01L21/76858 , H01L21/76865 , H01L21/76867 , H01L21/76895 , H01L23/485 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi3, CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.
摘要翻译：本发明属于集成半导体电路的技术领域，涉及在不超过32nm的工艺中使用的方法来提高Cu互连的电迁移率。铜互连上的涂层如CuSi3，CuGe和CuSiN可以通过自动配准来制备，并且通过使用新的不透水层材料，可以大大提高Cu互连的电迁移电阻，并且可以保持高导电性，这为不超过32nm的工艺节点的互连工艺提供了理想的解决方案。

7. 发明申请

US20130078793A1 METHOD FOR DEPOSITING A GATE OXIDE AND A GATE ELECTRODE SELECTIVELY 审中-公开
标题翻译：选择选择氧化铝和门电极的方法
公开(公告)号：US20130078793A1
公开(公告)日：2013-03-28
申请号：US13528446
申请日：2012-06-20
申请人： Qingqing Sun , Ye Li , Runchen Fang , Pengfel Wang , Wei Zhang
发明人： Qingqing Sun , Ye Li , Runchen Fang , Pengfel Wang , Wei Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/02178 , H01L21/02164 , H01L21/02181 , H01L21/02307 , H01L21/28194 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66583
摘要： The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO2 so as to reduce the difficulty of the etching process and increase the production efficiency.
摘要翻译：本发明属于集成半导体电路的技术领域，并且涉及选择性地沉积栅极氧化物和栅电极的方法。本发明利用十八烷基三乙氧基硅烷（ODTS'）易于连接Si-OH界面并难以附着于Si-H界面，并选择性地沉积栅极氧化物和栅电极材料，从而避免不必要的材料浪费并节约成本。同时，本发明将栅极氧化物和栅电极的蚀刻转移到SiO 2的蚀刻中，以减少蚀刻工艺的难度并提高生产效率。

8. 发明申请

US20140167134A1 SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：自对准垂直非线性半导体存储器件
公开(公告)号：US20140167134A1
公开(公告)日：2014-06-19
申请号：US13514032
申请日：2012-02-02
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , G11C16/0475 , H01L21/84 , H01L27/1021 , H01L27/1026 , H01L27/1157 , H01L27/1203 , H01L29/7391 , H01L29/7923 , H01L29/8616
摘要： The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density.
摘要翻译：本发明属于半导体存储器件的技术领域，具体涉及一种自对准的垂直非易失性半导体存储器件，包括：半导体衬底，第一掺杂类型的漏极区域，第二掺杂型的两个源极区域，用于捕获电子的堆叠栅; 其中漏极区域，两个源极区域和堆叠的栅极形成共享一个栅极和一个漏极的两个隧道场效应晶体管（TFET），每个TFET的漏极区域电流受到电荷的量和分布的影响用于捕获电子的堆叠栅极，漏极埋在半导体衬底中，漏极区域上方的源极区域通过沟道与漏极分离，并通过第一掺杂类型的区域彼此分离。本发明的半导体存储器件具有小的单位面积和简单的制造工艺。使用本发明的存储芯片的制造成本低，存储密度高。

9. 发明申请

US20140034891A1 SEMICONDUCTOR MEMORY STRUCTURE AND ITS MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器结构及其制造方法
公开(公告)号：US20140034891A1
公开(公告)日：2014-02-06
申请号：US13376994
申请日：2011-08-15
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/24
CPC分类号： H01L27/2463 , H01L27/2445 , H01L27/2472 , H01L29/7391 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.
摘要翻译：本发明属于微电子器件的技术领域，具体涉及一种半导体存储器结构及其制造方法。形成通过隧道场效应晶体管对相变存储器或电阻变化存储器进行擦除，写入和读取操作的半导体存储器结构，一方面，当电流通过隧道场效应晶体管时， pn结积极偏置，满足擦除和写入相变存储器和电阻变化存储器的高电流要求，另一方面，场效应晶体管的垂直结构可以大大提高存储器件阵列的密度。本发明还公开了一种非常适用于存储芯片的方法，用于使用自对准工艺制造半导体存储器结构。

10. 发明授权

US08574958B2 Method for manufacturing a gate-control diode semiconductor memory device 有权
标题翻译：栅极控制二极管半导体存储器件的制造方法
公开(公告)号：US08574958B2
公开(公告)日：2013-11-05
申请号：US13535032
申请日：2012-06-27
申请人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/7391 , H01L29/8616
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，并配置了简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成npnp掺杂结构，浮动门中的电荷决定了器件的阈值电压，从而实现了存储器的功能。本发明具有制造栅极控制二极管存储器件的能力，其能够通过高驱动电流和小的次级阈值摆动的优点来降低芯片功耗。本发明适用于基于柔性基板和平板显示器和浮动栅极存储器等的半导体器件制造。

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