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1. 发明申请

US20140282286A1 ETCH FAILURE PREDICTION BASED ON WAFER RESIST TOP LOSS 有权
标题翻译：基于波浪失效的失效预测失败
公开(公告)号：US20140282286A1
公开(公告)日：2014-09-18
申请号：US13835339
申请日：2013-03-15
申请人： Qing YANG , Shyue Fong Quek , Gek Soon Chua , Yee Mei Foong , Dong Qing Zhang , Yun Tang
发明人： Qing YANG , Shyue Fong Quek , Gek Soon Chua , Yee Mei Foong , Dong Qing Zhang , Yun Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G03F1/70 , G03F7/70433 , G03F7/705
摘要： An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.
摘要翻译：公开了一种用于方法学和相关设备的方法，其使模拟过程能够检查设计的完整性并且预测所产生的电路的可制造性，其考虑到处理纬度而没有长的周转时间和/或高技能的工程师。实施例包括：确定IC设计的第一和第二特征; 基于IC设计的空中图像确定IC设计的抗蚀剂层的厚度; 根据厚度确定阈值; 以及将阈值与第一和第二特征之间的间隔距离进行比较。

2. 发明授权

US08898597B2 Etch failure prediction based on wafer resist top loss 有权
标题翻译：基于晶圆抗蚀剂顶部损耗的蚀刻失效预测
公开(公告)号：US08898597B2
公开(公告)日：2014-11-25
申请号：US13835339
申请日：2013-03-15
申请人： Qing Yang , Shyue Fong Quek , Gek Soon Chua , Yee Mei Foong , Dong Qing Zhang , Yun Tang
发明人： Qing Yang , Shyue Fong Quek , Gek Soon Chua , Yee Mei Foong , Dong Qing Zhang , Yun Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G03F1/70 , G03F7/70433 , G03F7/705
摘要： An approach for methodology, and an associated apparatus, enabling a simulation process to check integrity of the design and predict a manufacturability of a resulting circuit that accounts for process latitude without a long turnaround time and/or a highly skilled engineer is disclosed. Embodiments include: determining first and second features of an IC design; determining a thickness of a resist layer of the IC design based on an aerial image of the IC design; determining a threshold value according to the thickness; and comparing the threshold value to a separation distance between the first and second features.
摘要翻译：公开了一种用于方法学和相关设备的方法，其使模拟过程能够检查设计的完整性并且预测所产生的电路的可制造性，其考虑到处理纬度而没有长的周转时间和/或高技能的工程师。实施例包括：确定IC设计的第一和第二特征; 基于IC设计的空中图像确定IC设计的抗蚀剂层的厚度; 根据厚度确定阈值; 以及将阈值与第一和第二特征之间的间隔距离进行比较。

3. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

4. 发明授权

US06465296B1 Vertical source/drain contact semiconductor 有权
标题翻译：垂直源极/漏极接触半导体
公开(公告)号：US06465296B1
公开(公告)日：2002-10-15
申请号：US10167095
申请日：2002-06-10
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L218238
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.
摘要翻译：提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

5. 发明授权

US06406994B1 Triple-layered low dielectric constant dielectric dual damascene approach 有权
标题翻译：三层低介电常数电介质双镶嵌方法
公开(公告)号：US06406994B1
公开(公告)日：2002-06-18
申请号：US09726657
申请日：2000-11-30
申请人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
IPC分类号： H01L2144
CPC分类号： B41M5/5254 , B41M5/508 , B41M5/5218 , B41M5/5272 , Y10T428/24802
摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
摘要翻译：描述了三层低介电常数材料双镶嵌金属化工艺。金属线被覆盖在半导体衬底上的绝缘层所覆盖。第一类型的第一介电层沉积在绝缘层上。第二类型的第二介电层沉积在第一介电层上。通孔图案被蚀刻到第二介电层中。此后，第一类型的第三电介质层沉积在图案化的第二介电层上。同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

6. 发明授权

US06275089B1 Low voltage controllable transient trigger network for ESD protection 有权
标题翻译：低电压可控瞬态触发网络，用于ESD保护
公开(公告)号：US06275089B1
公开(公告)日：2001-08-14
申请号：US09482048
申请日：2000-01-13
申请人： Jun Song , Ting Cheong Ang , Shyue Fong Quek , Lap Chan
发明人： Jun Song , Ting Cheong Ang , Shyue Fong Quek , Lap Chan
IPC分类号： H03K508
CPC分类号： H01L27/0251
摘要： A transient protection circuit is described which provides electrostatic discharge (ESD) protection for an internal circuit of an IC. The transient protection circuit comprises two Zener diodes connected in series between the input pad and the internal circuit of the IC. A sufficiently large ESD pulse will drive one the two Zener diodes into breakdown mode, thereby reducing the magnitude of the ESD pulse to the remainder of the circuit. Resistive means are paralleled with the Zener diodes to provide a signal path at non-ESD voltages. To help shunt the ESD current away from the internal circuit, PMOS and NMOS transistors are connected in parallel between the positive and the negative voltage supply and their junction is connected to the internal circuit. Negative ESD pulses cause the PMOS transistors to turn on, dumping the ESD energy into the positive voltage supply, while positive ESD pulses cause the NMOS transistors to turn on, dumping the ESD energy into the negative voltage supply. Voltage changes, caused by currents flowing through the resistive means, trigger parasitic SCRs into conduction to provide the bulk of the ESD protection.
摘要翻译：描述了为IC的内部电路提供静电放电（ESD）保护的瞬态保护电路。瞬态保护电路包括串联连接在输入焊盘和IC内部电路之间的两个齐纳二极管。足够大的ESD脉冲将驱动两个齐纳二极管中的一个进入击穿模式，从而将ESD脉冲的幅度减小到电路的其余部分。电阻性装置与齐纳二极管并联，以在非ESD电压下提供信号路径。为了有助于将ESD电流从内部电路分流，PMOS和NMOS晶体管并联连接在正电压和负电源之间，它们的结连接到内部电路。负ESD脉冲导致PMOS晶体管导通，将ESD能量转储到正电压源中，而正的ESD脉冲使NMOS晶体管导通，将ESD能量转储到负电源。由电流流过电阻的电流引起的电压变化会将寄生的SCR触发导通，以提供大量的ESD保护。

7. 发明授权

US06258677B1 Method of fabricating wedge isolation transistors 失效
标题翻译：楔形隔离晶体管的制造方法
公开(公告)号：US06258677B1
公开(公告)日：2001-07-10
申请号：US09409875
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/76264 , H01L21/76278 , H01L21/76283 , H01L21/823878 , H01L29/41783 , H01L29/66545 , H01L29/66628 , H01L29/66651
摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要翻译：一种制造晶体管的方法，包括以下步骤。提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。在活性区域上生长外延硅以形成SEG区域。在SEG区域上形成一个虚拟门。凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。去除虚拟栅极，暴露凸起的外延硅层的内侧壁。在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间。在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间形成栅极导体。去除侧壁间隔物。不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

8. 发明授权

US06248618B1 Method of fabrication of dual gate oxides for CMOS devices 有权
标题翻译：制造CMOS器件双栅氧化物的方法
公开(公告)号：US06248618B1
公开(公告)日：2001-06-19
申请号：US09415246
申请日：1999-10-12
申请人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , Y10S438/981
摘要： A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.
摘要翻译：一种形成厚薄的栅极氧化物的方法，包括以下步骤。提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

9. 发明授权

US06963113B2 Method of body contact for SOI MOSFET 有权
标题翻译： SOI MOSFET的体接触方法
公开(公告)号：US06963113B2
公开(公告)日：2005-11-08
申请号：US10915670
申请日：2004-08-10
申请人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
发明人： Ting Cheong Ang , Sang Yee Loong , Shyue Fong Quek , Jun Song
IPC分类号： H01L21/336 , H01L29/786 , H01L29/76
CPC分类号： H01L29/66772 , H01L29/78615
摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.
摘要翻译：描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。第一和第二沟槽填充有绝缘层。栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。沉积覆盖栅电极的层间电介质层。第一触点通过层间介质层开放到下面的源极和漏极区域。在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

10. 发明授权

US06582856B1 Simplified method of fabricating a rim phase shift mask 失效
标题翻译：制造轮辋相移掩模的简化方法
公开(公告)号：US06582856B1
公开(公告)日：2003-06-24
申请号：US09513872
申请日：2000-02-28
申请人： Shyue Fong Quek , Ting Cheong Ang , Jun Song , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Jun Song , Sang Yee Loong
IPC分类号： G03F900
CPC分类号： G03F1/29
摘要： A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.
摘要翻译：实现了制作边缘相移掩模的新方法。在透明基底上方设置不透明层。将抗蚀剂层沉积在不透明层上。抗蚀剂层被图案化。蚀刻不透明层和透明基板。抗蚀剂层掩盖该蚀刻。在该蚀刻期间蚀刻不透明层。因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。在相移层实施例中也可以使用蚀刻停止层。

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