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1. 发明授权

US07362645B2 Integrated circuit fuses having corresponding storage circuitry 有权
标题翻译：集成电路保险丝具有相应的存储电路
公开(公告)号：US07362645B2
公开(公告)日：2008-04-22
申请号：US10955356
申请日：2004-09-30
申请人： Qadeer A. Qureshi , John J. Vaglica , William C. Moyer , Ryan D. Bedwell
发明人： Qadeer A. Qureshi , John J. Vaglica , William C. Moyer , Ryan D. Bedwell
IPC分类号： G11C17/18 , G11C17/00 , G11C7/10 , G11C7/00
CPC分类号： G11C17/18
摘要： Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).
摘要翻译：存储电路（66）可以用于存储熔丝（77）的值，使得可以读取存储电路（66）而不是保险丝（77）。通过从存储电路（66）而不是保险丝（77）访问熔丝值，对熔断器（77）将没有感应电流可能导致尚未熔断的熔断器的边缘熔断器。这有助于防止未熔断的保险丝被错误地读取为已被吹灭的情况。因此，存储电路（66）的使用显着地提高了熔丝模块（20）的可靠性。对于一些实施例，可以使用选择存储电路（64）来确定是否可以读取存储电路（66），或者是否必须读取保险丝（77）之一以便检索所需的当前熔丝值。存储在存储电路（66）中的熔丝值也可以用作直接硬件信号（80）。

2. 发明授权

US06917555B2 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor 有权
标题翻译：集成电路电源管理，用于减少电路阵列中的漏电流及其方法
公开(公告)号：US06917555B2
公开(公告)日：2005-07-12
申请号：US10675005
申请日：2003-09-30
申请人： Ryan D. Bedwell , Christopher K. Y. Chun , Qadeer A. Qureshi , John J. Vaglica
发明人： Ryan D. Bedwell , Christopher K. Y. Chun , Qadeer A. Qureshi , John J. Vaglica
IPC分类号： G06F1/32 , G11C5/14 , G11C7/22 , G11C7/00
CPC分类号： G06F1/3275 , G06F1/3203 , G11C5/14 , G11C7/22 , G11C2207/2227 , Y02D10/14
摘要： Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.
摘要翻译：在具有与存储器阵列接口的处理器的处理系统的低功率模式期间，在存储器阵列中消除泄漏电流。因为创建了两个电源平面，所以处理器可以在阵列掉电时绕过存储器阵列，继续执行使用系统存储器的指令。开关选择性地去除与电源电压端子的电连接，以响应于执行指令或源自系统处于不同于处理器的系统的来源的处理器启动的控制。在恢复对存储器阵列的电力的情况下，取决于支持阵列到存储器阵列的两个电力平面中的哪一个位于何处，数据可能也可能不需要被标记为不可用。可以使用预定的标准来控制恢复电力的时间。可以实现多个阵列以独立地减少泄漏电流。

3. 发明授权

US07802038B2 Communication steering for use in a multi-master shared resource system 有权
标题翻译：用于多主共享资源系统的通信指导
公开(公告)号：US07802038B2
公开(公告)日：2010-09-21
申请号：US12276038
申请日：2008-11-21
申请人： Ryan D. Bedwell , Arnold R. Cruz , John J. Vaglica , William C. Moyer
发明人： Ryan D. Bedwell , Arnold R. Cruz , John J. Vaglica , William C. Moyer
IPC分类号： G06F13/00
CPC分类号： G06F13/364
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

4. 发明申请

US20090077291A1 COMMUNICATION STEERING FOR USE IN A MULTI-MASTER SHARED RESOURCE SYSTEM 有权
标题翻译：用于多主共享资源系统的通信方向
公开(公告)号：US20090077291A1
公开(公告)日：2009-03-19
申请号：US12276038
申请日：2008-11-21
申请人： Ryan D. Bedwell , Arnaldo R. Cruz , John J. Vaglica , William C. Moyer
发明人： Ryan D. Bedwell , Arnaldo R. Cruz , John J. Vaglica , William C. Moyer
IPC分类号： G06F13/40
CPC分类号： G06F13/364
摘要： New approaches for providing communication between multiple masters (12, 14) and one or more shared resources (24, 30, 100) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard (100). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry (402, 417, 480) may be used to provide steering for additional signals such as interrupts. Other shared resources (24, 30) may use more centralized circuitry (36) to perform a steering function for additional signals.
摘要翻译：需要用于在多个主机（12,14）和一个或多个共享资源（24,30,100）之间提供通信的新方法。可能需要共享的资源的一个例子是符合通用串行总线（USB）标准（100）的电路。 USB规范将USB端点定义为位于USB设备中的数据和控制通道。在一些情况下，期望具有由一个处理器控制的一定数量的端点以及由不同处理器控制的其他端点，从而提供对所有端点的共享控制。电路（402,417,480）可用于为诸如中断的附加信号提供转向。其他共享资源（24,30）可以使用更集中的电路（36）来执行附加信号的转向功能。

5. 发明授权

US08935574B2 Correlating traces in a computing system 有权
标题翻译：计算系统中的相关跟踪
公开(公告)号：US08935574B2
公开(公告)日：2015-01-13
申请号：US13328512
申请日：2011-12-16
申请人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
发明人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
IPC分类号： G06F11/00
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/835 , G06F2201/88
摘要： An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
摘要翻译：用于同步跟踪数据的装置，处理器和方法。处理器包括多个核心，并且每个核心以不同的本地时钟频率运行。全局时钟分配给每个核心，并使用全局时钟和本地时钟生成时间戳。时间戳和本地时钟饱和值包含在每个跟踪条目中，本地时钟饱和值等于本地时钟与全局时钟之间的比率。基于时间戳和本地时钟饱和度值，来自独立核心的跟踪条目在后处理阶段是时间相关的。

6. 发明申请

US20130159780A1 CORRELATING TRACES IN A COMPUTING SYSTEM 有权
标题翻译：计算系统中的相关跟踪
公开(公告)号：US20130159780A1
公开(公告)日：2013-06-20
申请号：US13328512
申请日：2011-12-16
申请人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
发明人： Ryan D. Bedwell , Elizabeth M. Cooper , Eric M. Rentschler
IPC分类号： G06F11/34
CPC分类号： G06F11/3466 , G06F11/3419 , G06F11/348 , G06F2201/835 , G06F2201/88
摘要： An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.
摘要翻译：用于同步跟踪数据的装置，处理器和方法。处理器包括多个核心，并且每个核心以不同的本地时钟频率运行。全局时钟分配给每个核心，并使用全局时钟和本地时钟生成时间戳。时间戳和本地时钟饱和值包含在每个跟踪条目中，本地时钟饱和值等于本地时钟与全局时钟之间的比率。基于时间戳和本地时钟饱和度值，来自独立核心的跟踪条目在后处理阶段是时间相关的。

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