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1. 发明申请

US20170060750A1 CACHE WAY PREDICTION USING PARTIAL TAGS 审中-公开
标题翻译：使用部分标签缓存预测
公开(公告)号：US20170060750A1
公开(公告)日：2017-03-02
申请号：US14843958
申请日：2015-09-02
申请人： QUALCOMM Incorporated
发明人： Anil KRISHNA , Gregory Michael WRIGHT , Derek Robert HOWER
IPC分类号： G06F12/08
CPC分类号： G06F12/0895 , G06F2212/1021
摘要： Method and apparatus for cache way prediction using a plurality of partial tags are provided. In a cache-block address comprising a plurality of sets and a plurality of ways or lines, one of the sets is selected for indexing, and a plurality of distinct partial tags are identified for the selected set. A determination is made as to whether a partial tag for a new line collides with any of the partial tags for current resident lines in the selected set. If the partial tag for the new line does not collide with any of the partial tags for the current resident lines, then there is no aliasing. If the partial tag for the new line collides with any of the partial tags for the current resident lines, then aliasing may be avoided by reading the full tag array and updating the partial tags.
摘要翻译：提供了使用多个部分标签的高速缓存方式预测的方法和装置。在包括多个集合和多个方式或行的高速缓存块地址中，选择该集合中的一个用于索引，并为所选择的集合识别多个不同的部分标签。确定新行的部分标签是否与所选集合中当前居民行的任何部分标签相冲突。如果新行的部分标签不与当前居民行的任何部分标签相冲突，则不存在别名。如果新行的部分标签与当前驻留行的任何部分标签相冲突，则可以通过读取完整标记数组并更新部分标签来避免混叠。

2. 发明申请

US20180074568A1 METHOD AND APPARATUS FOR DYNAMIC CLOCK AND VOLTAGE SCALING IN A COMPUTER PROCESSOR BASED ON PROGRAM PHASE 审中-公开
公开(公告)号：US20180074568A1
公开(公告)日：2018-03-15
申请号：US15814361
申请日：2017-11-15
申请人： QUALCOMM Incorporated
发明人： Shivam PRIYADARSHI , Anil KRISHNA , Raguram DAMODARAN , Jeffrey Todd BRIDGES , Ryan WELLS , Norman GARGASH , Rodney Wayne SMITH
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

3. 发明申请

US20170060593A1 HIERARCHICAL REGISTER FILE SYSTEM 审中-公开
标题翻译：分层寄存器文件系统
公开(公告)号：US20170060593A1
公开(公告)日：2017-03-02
申请号：US14843921
申请日：2015-09-02
申请人： QUALCOMM Incorporated
发明人： Anil KRISHNA , Rodney Wayne SMITH , Sandeep Suresh NAVADA , Shivam PRIYADARSHI , Niket Kumar CHOUDHARY , Raguram DAMODARAN
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30105 , G06F9/30138 , G06F9/384 , G06F9/3867
摘要： Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.
摘要翻译：系统和方法涉及包括1级物理寄存器文件（L1 PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。识别在处理器的指令流水线中执行的指令的生成的子集，其具有用于一个或多个未来指令的高似然性。生产的子集存储在L1 PRF中，而所有生产都存储在后备PRF中。

4. 发明申请

US20190087184A1 SELECT IN-ORDER INSTRUCTION PICK USING AN OUT OF ORDER INSTRUCTION PICKER 审中-公开
公开(公告)号：US20190087184A1
公开(公告)日：2019-03-21
申请号：US15706540
申请日：2017-09-15
申请人： QUALCOMM Incorporated
发明人： Vignyan Reddy KOTHINTI NARESH , Lisa HSU , Vinay MURTHY , Anil KRISHNA , Gregory WRIGHT, III
IPC分类号： G06F9/30 , G06F9/38
摘要： Systems and methods are directed to instruction execution in a computer system having an out of order instruction picker, which are typically used in computing systems capable of executing multiple instructions in parallel. Such systems are typically block based and multiple instructions are grouped in execution units such as Reservation Station (RSV) Arrays. If an event, such as an exception, page fault, or similar event occurs, the block may have to be swapped out, that is removed from execution, until the event clears. Typically when the event clears the block is brought back to be executed, but typically will be assigned a different RSV Array and re-executed from the beginning of the block. Tagging instructions that may cause such events and then untagging them, by resetting the tag, once they have executed can eliminate much of the typical unnecessary re-execution of instructions.

5. 发明申请

US20150019843A1 METHOD AND APPARATUS FOR SELECTIVE RENAMING IN A MICROPROCESSOR 有权
标题翻译：微处理器中选择性还原的方法和装置
公开(公告)号：US20150019843A1
公开(公告)日：2015-01-15
申请号：US14091340
申请日：2013-11-27
申请人： QUALCOMM Incorporated
发明人： Anil KRISHNA , Sandeep S. NAVADA , Niket K. CHOUDHARY , Michael Scott MCILVAINE , Thomas Andrew SARTORIUS , Rodney Wayne SMITH , Kenneth Alan DOCKSER
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3824 , G06F9/3842 , G06F9/3855 , G06F9/3861
摘要： A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.
摘要翻译：本文公开了一种允许无序处理器重用使用中物理寄存器的方法和装置。该方法和装置使用诸如重命名映射表（RMT）和物理寄存器文件（PRF）中的令牌和/或其他标识符的标识符来指示是否允许或不允许将指令结果写入物理寄存器。

6. 发明申请

US20180081806A1 MEMORY VIOLATION PREDICTION 审中-公开
公开(公告)号：US20180081806A1
公开(公告)日：2018-03-22
申请号：US15273182
申请日：2016-09-22
申请人： QUALCOMM Incorporated
发明人： Vignyan Reddy KOTHINTI NARESH , Anil KRISHNA , Gregory Michael WRIGHT
IPC分类号： G06F12/0815 , G06F9/30
CPC分类号： G06F12/0862 , G06F9/3834 , G06F9/3842 , G06F2212/1021 , G06F2212/1032 , G06F2212/452 , G06F2212/6022 , G06F2212/6028
摘要： Disclosed are methods and apparatuses for preventing memory violations. In an aspect, a fetch unit accesses, from a branch predictor of a processor, a disambiguation indicator associated with a block of instructions of a program to be executed by the processor, and fetches, from an instruction cache, the block of instructions. The processor executes load instructions and/or store instructions in the block of instructions based on the disambiguation indicator indicating whether or not the load instructions and/or the store instructions in the block of instructions can bypass other instructions of the program or be bypassed by other instructions of the program.

7. 发明申请

US20170090508A1 METHOD AND APPARATUS FOR EFFECTIVE CLOCK SCALING AT EXPOSED CACHE STALLS 审中-公开
公开(公告)号：US20170090508A1
公开(公告)日：2017-03-30
申请号：US14865092
申请日：2015-09-25
申请人： QUALCOMM Incorporated
发明人： Shivam PRIYADARSHI , Anil KRISHNA , Raguram DAMODARAN , Jeffrey Todd BRIDGES , Thomas Philip SPEIER , Rodney Wayne SMITH , Keith Alan BOWMAN , David Joseph Winston HANSQUINE
IPC分类号： G06F1/08 , G06F12/12 , G06F12/08
CPC分类号： G06F1/08 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F12/0804 , G06F12/0875 , G06F12/0897 , G06F12/12 , G06F2212/1024 , G06F2212/60 , Y02D10/126 , Y02D10/152
摘要： The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

8. 发明申请

US20150268959A1 PHYSICAL REGISTER SCRUBBING IN A COMPUTER MICROPROCESSOR 审中-公开
标题翻译：计算机微处理器中的物理寄存器刷新
公开(公告)号：US20150268959A1
公开(公告)日：2015-09-24
申请号：US14221430
申请日：2014-03-21
申请人： QUALCOMM Incorporated
发明人： Anil KRISHNA , Weidan WU , Sandeep Suresh NAVADA , Niket Kumar CHOUDHARY , Rodney Wayne SMITH
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30098 , G06F9/3832 , G06F9/3838 , G06F9/384 , G06F9/3861
摘要： Identifying two instructions without intervening potential pipeline flushers that write to the same architected destination register in order to free the physical register corresponding to the older of the two instructions.
摘要翻译：识别两个指令，而不会插入写入同一架构目标寄存器的潜在管道冲洗器，以便释放与两个指令中较旧的对应的物理寄存器。

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