专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10636962B2 Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching, suitable for use in memory systems for storing data 有权
公开(公告)号：US10636962B2
公开(公告)日：2020-04-28
申请号：US16107484
申请日：2018-08-21
申请人： QUALCOMM Incorporated
发明人： Chando Park , Sungryul Kim , Seung Hyuk Kang
IPC分类号： H01L43/02 , H01L43/10 , H01L43/12 , H01F10/32 , G11C11/16 , H01L27/22
CPC分类号： H01L43/02 , G11C11/161 , H01F10/3254 , H01F10/3286 , H01L27/228 , H01L43/10 , H01L43/12 , G11C11/1657 , G11C11/1673 , G11C11/1675
摘要： Aspects disclosed include spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching. A free layer in a MTJ in the SOT-MTJ device includes both a perpendicular magnetic anisotropy (PMA) region(s) and an in-plane magnetic anisotropy (IMA) region(s). A spin torque is generated in the free layer when a SOT switching current flows through an electrode adjacent to the free layer sufficient to switch the magnetic moment of the free layer to an in-plane magnetic orientation. To prevent a non-deterministic perpendicular magnetic orientation after the SOT switching current is removed, the free layer also includes the IMA region(s) to provide an in-plane magnetization to generate an effective magnetic field in the free layer to assist in switching the magnetic moment of the free layer past an in-plane magnetic orientation to a perpendicular magnetic orientation.

2. 发明授权

US10381060B2 High-speed, low power spin-orbit torque (SOT) assisted spin-transfer torque magnetic random access memory (STT-MRAM) bit cell array 有权
公开(公告)号：US10381060B2
公开(公告)日：2019-08-13
申请号：US15247791
申请日：2016-08-25
申请人： QUALCOMM Incorporated
发明人： Jimmy Jianan Kan , Chando Park , Peiyuan Wang , Sungryul Kim , Seung Hyuk Kang
IPC分类号： G11C11/16 , H01L27/22
摘要： A magnetic random access memory (MRAM) array including several bit cells is described. Each of the bit cells may include a perpendicular magnetic tunnel junction (pMTJ) including a reference layer, a barrier layer supporting the reference layer, and a free layer supporting the barrier layer. A spin-hall conductive material layer may support the free layer. A driver may be operable to set a state of at least one of the bit cells using an increased spin-transfer torque (STT) current and a spin-hall effect from the spin-hall conductive material layer. The increased STT current may be driven through the spin-hall conductive material layer and the pMTJ so that a spin current is generated from the reference layer and the spin-hall conductive material layer.

3. 发明授权

US10263645B2 Error correction and decoding 有权
公开(公告)号：US10263645B2
公开(公告)日：2019-04-16
申请号：US15716451
申请日：2017-09-26
申请人： QUALCOMM Incorporated
发明人： Seong-Ook Jung , Sara Choi , Byung Kyu Song , Taehui Na , Jisu Kim , Jung Pill Kim , Sungryul Kim , Taehyun Kim , Seung Hyuk Kang
IPC分类号： H03M13/00 , G06F11/10 , H03M13/15
摘要： In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

4. 发明授权

US09612908B2 Performing memory data scrubbing operations in processor-based memory in response to periodic memory controller wake-up periods 有权
公开(公告)号：US09612908B2
公开(公告)日：2017-04-04
申请号：US14627268
申请日：2015-02-20
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Sungryul Kim , Jung Pill Kim
IPC分类号： G06F11/00 , G06F11/14 , G06F12/02 , G06F11/10
CPC分类号： G06F11/1402 , G06F11/106 , G06F12/023 , G06F12/0238 , G06F2201/805 , G06F2212/7205 , Y02D10/13
摘要： Aspects of the disclosure involve memory data scrubber circuits configured to perform memory data scrubbing operations in a processor-based memory to provide data error correction in response to periodic memory controller wake-up periods. Memory data scrubbing is performed to correct errors in data words stored in memory. Memory data scrubbing is initiated in the memory to conserve power in response to periodic memory controller wake-up periods during processor idle periods. Further, in certain aspects disclosed herein, the memory data scrubber circuit is provided as a separate system outside of the memory controller in the memory system. In this manner, power consumption can be further reduced, because the memory data scrubber circuit can continue with memory data scrubbing operations in the memory independent of the memory controller operation, and after the memory controller access commands issued during the wake-up period are completed and the memory controller is powered-down.

5. 发明授权

US09583170B2 Adjusting resistive memory write driver strength based on a mimic resistive memory write operation 有权
标题翻译：基于模拟电阻式存储器写入操作调整电阻式存储器写入驱动器强度
公开(公告)号：US09583170B2
公开(公告)日：2017-02-28
申请号：US14620487
申请日：2015-02-12
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Jung Pill Kim , Sungryul Kim
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00
CPC分类号： G11C11/1675 , G11C11/1677 , G11C2013/0078
摘要： Aspects of adjusting resistive memory write driver strength based on a mimic resistive memory write operation are disclosed. In one aspect, a write driver adjustment circuit is provided to adjust a write current provided by a write driver to a resistive memory for write operations. The write driver adjustment circuit includes a mimic write driver configured to provide a mimic write current that mimics the write current provided to the resistive memory. The mimic write current is applied to a mimic resistive memory that contains mimic resistive memory elements that mimic a resistance distribution of the resistive memory. When the mimic write current is applied, a mimic voltage is generated across the mimic resistive memory elements. The write driver adjustment circuit is configured to adjust the write current based on the mimic voltage so that the write current is sufficient for write operations, but low enough to reduce breakdown.
摘要翻译：公开了基于模拟电阻式存储器写入操作来调节电阻性存储器写入驱动器强度的方面。一方面，提供写入驱动器调整电路以将由写入驱动器提供的写入电流调整到用于写入操作的电阻性存储器。写驱动器调整电路包括模拟写驱动器，其配置为提供模拟写入电流，模拟写入电流提供给电阻存储器。模拟写入电流被施加到模拟电阻性存储器，其包含模拟电阻性存储器的电阻分布的模拟电阻存储器元件。当应用模拟写入电流时，在模拟电阻存储器元件之间产生模拟电压。写入驱动器调整电路被配置为基于模拟电压来调整写入电流，使得写入电流对于写入操作是足够的，但是足够低以减少击穿。

6. 发明申请

US20160267959A1 WRITE DRIVER CIRCUITS FOR RESISTIVE RANDOM ACCESS MEMORY (RAM) ARRAYS 有权
标题翻译：用于电阻随机存取存储器（RAM）阵列的写驱动电路
公开(公告)号：US20160267959A1
公开(公告)日：2016-09-15
申请号：US14644631
申请日：2015-03-11
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Sungryul Kim , Taehyun Kim
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.
摘要翻译：在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

7. 发明授权

US09275714B1 Read operation of MRAM using a dummy word line 有权
标题翻译：使用虚拟字线读取MRAM的操作
公开(公告)号：US09275714B1
公开(公告)日：2016-03-01
申请号：US14499050
申请日：2014-09-26
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Sungryul Kim , Jung Pill Kim , Xiangyu Dong
IPC分类号： G11C11/16
CPC分类号： G11C11/1673 , G11C11/161 , G11C11/1693
摘要： Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM). Prior to determining whether there is a hit in the MRAM for a first address corresponding to the read operation, a dummy word line is activated, based on at least a subset of bits of the first address. A settling process for a reference voltage for reading MRAM bit cells at the first address is initiated, based on dummy cells connected to the dummy word line and a settled reference voltage is obtained. If there is a hit, a first word line is activated based on a row address determined from the first address, and the MRAM bit cells at the first address are read using the settled reference voltage.
摘要翻译：系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的位的至少一个子集，激活伪字线。基于与虚拟字线连接的虚拟单元，启动用于读取第一地址的MRAM位单元的参考电压的稳定处理，并获得稳定的参考电压。如果存在命中，则基于从第一地址确定的行地址来激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

8. 发明授权

US09583171B2 Write driver circuits for resistive random access memory (RAM) arrays 有权
标题翻译：为电阻随机存取存储器（RAM）阵列写入驱动电路
公开(公告)号：US09583171B2
公开(公告)日：2017-02-28
申请号：US14644631
申请日：2015-03-11
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Sungryul Kim , Taehyun Kim
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/1653 , G11C11/1655 , G11C11/1659 , G11C13/0023 , G11C13/0026 , G11C13/0069 , G11C2013/0073 , G11C2213/79 , G11C2213/82
摘要： Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.
摘要翻译：在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

9. 发明授权

US09552244B2 Real time correction of bit failure in resistive memory 有权
标题翻译：电阻存储器中位故障的实时校正
公开(公告)号：US09552244B2
公开(公告)日：2017-01-24
申请号：US14150559
申请日：2014-01-08
申请人： QUALCOMM Incorporated
发明人： Taehyun Kim , Sungryul Kim , Jung Pill Kim
IPC分类号： G06F11/07 , H03M13/05 , G06F11/10 , G11C29/00 , G11C29/04
CPC分类号： G06F11/0766 , G06F11/1008 , G11C29/808 , G11C29/814 , G11C2029/0411 , H03M13/05
摘要： Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.
摘要翻译：用于校正电阻存储器件中的位故障的系统和方法包括将存储器件划分成第一存储体和第二存储体。第一单位修复（SBR）阵列存储在第二存储体中，其中第一SBR阵列被配置为在第一存储体的第一行中的第一故障位中存储故障的第一指示。第一存储器组和第一SBR阵列被配置为在存储器访问操作期间并行访问。类似地，存储在第一存储体中的第二SBR阵列可以存储位在第二存储体中的故障的指示，其中可以并行地访问第二SBR阵列和第二存储体。因此，可以实时地校正第一和第二存储体中的位故障。

10. 发明授权

US09495261B2 Systems and methods for reducing memory failures 有权
标题翻译：减少内存故障的系统和方法
公开(公告)号：US09495261B2
公开(公告)日：2016-11-15
申请号：US14458009
申请日：2014-08-12
申请人： QUALCOMM Incorporated
发明人： Jung Pill Kim , Dexter Tamio Chun , Deepti Vijayalakshmi Sriramagiri , Mosaddiq Saifuddin , Xiangyu Dong , Sungryul Kim , Yanru Li , Jungwon Suh
IPC分类号： G06F11/00 , G06F11/20 , G11C29/52 , G06F11/08 , G06F11/30 , G11C29/44 , G11C29/04
CPC分类号： G06F11/2053 , G06F11/073 , G06F11/0775 , G06F11/0793 , G06F11/08 , G06F11/1048 , G06F11/3037 , G11C29/4401 , G11C29/52 , G11C2029/0409
摘要： Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.
摘要翻译：提供了修复或尝试修复存储器件中的随机位故障的系统内修复过程的方法和系统。在一些示例中，系统内修复过程可以根据故障是可校正还是不可校正来选择替代步骤。在这些示例中，该过程使用片上系统与存储器之间的通信来在正常操作期间修复故障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式