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1. 发明授权

US09096939B2 Electrolysis transistor 有权
标题翻译：电解晶体管
公开(公告)号：US09096939B2
公开(公告)日：2015-08-04
申请号：US12156178
申请日：2008-05-29
申请人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
发明人： Umesh Mishra , Rakesh Lai , Likun Shen , Lee McCarthy , Primit Parikh
IPC分类号： C25B9/00 , C25B9/04 , C02F1/461 , C25B1/02 , C25B11/00 , C25B15/00 , C25B11/04 , C25B1/00 , C25B1/04 , C25B1/06
CPC分类号： C25B1/02 , C25B1/003 , C25B1/04 , C25B1/06 , C25B9/04 , C25B11/00 , C25B11/0447 , C25B15/00 , Y02E60/366 , Y02P20/135
摘要： An electrolysis transistor for providing high-density electrochemistry and products utilizing the same, and high-efficiency electrolysis and electrochemical processes is disclosed. The electrolysis transistor may comprise an electrolyte, one or more working electrodes for transferring charge to or from said electrolyte, and one or more gate structures for altering electrode over-voltage and modifying the barrier at the electrode-electrolyte interface, reducing the voltage necessary for electrolysis. An electrochemical or photo-electrochemical cell may incorporate one or more of these electrolysis transistors.
摘要翻译：公开了一种用于提供高密度电化学的电解晶体管和利用其的产品，以及高效电解和电化学方法。电解晶体管可以包括电解质，用于将电荷转移到所述电解质或从所述电解质转移电荷的一个或多个工作电极，以及用于改变电极过电压并改变电极 - 电解质界面处的阻挡层的一个或多个栅极结构，电解。电化学或光电化学电池可并入这些电解晶体管中的一种或多种。

2. 发明申请

US20110193619A1 SEMICONDUCTOR ELECTRONIC COMPONENTS AND CIRCUITS 有权
标题翻译：半导体电子元件和电路
公开(公告)号：US20110193619A1
公开(公告)日：2011-08-11
申请号：US12701458
申请日：2010-02-05
申请人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
发明人： Primit Parikh , James Honea , Carl C. Blake, JR. , Robert Coffie , Yifeng Wu , Umesh Mishra
IPC分类号： H03K3/01 , H01L27/06
CPC分类号： H01L27/0883 , H01L21/8258 , H01L23/49562 , H01L23/49575 , H01L23/642 , H01L23/647 , H01L25/165 , H01L25/18 , H01L27/0605 , H01L2224/48137 , H01L2224/48195 , H01L2224/48247 , H01L2224/48257 , H01L2924/1305 , H01L2924/13055 , H01L2924/13062 , H01L2924/13091 , H01L2924/30107 , H03K17/567 , H01L2924/00
摘要： An electronic component includes a high-voltage depletion-mode transistor and a low-voltage enhancement-mode transistor both encased in a single package. A source electrode of the high-voltage depletion-mode transistor is electrically connected to a drain electrode of the low-voltage enhancement-mode transistor, a drain electrode of the high-voltage depletion-mode transistor is electrically connected to a drain lead of the single package, a gate electrode of the low-voltage enhancement-mode transistor is electrically connected to a gate lead of the single package, a gate electrode of the high-voltage depletion-mode transistor is electrically connected to an additional lead of the single package, and a source electrode of the low-voltage enhancement-mode transistor is electrically connected to a conductive structural portion of the single package.
摘要翻译：电子部件包括高压耗尽型晶体管和低压增强型晶体管，两者都封装在单个封装中。高电压耗尽型晶体管的源电极电连接到低电压增强型晶体管的漏电极，高电压耗尽型晶体管的漏极电连接到漏极引线单个封装，低电压增强型晶体管的栅电极电连接到单个封装的栅极引线，高电压耗尽型晶体管的栅极电连接到单个封装的附加引线并且低电压增强型晶体管的源电极电连接到单个封装的导电结构部分。

3. 发明申请

US20110127541A1 SEMICONDUCTOR HETEROSTRUCTURE DIODES 有权
标题翻译：半导体结构二极管
公开(公告)号：US20110127541A1
公开(公告)日：2011-06-02
申请号：US13008874
申请日：2011-01-18
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/02
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

4. 发明申请

US20110114997A1 HIGH VOLTAGE GaN TRANSISTORS 有权
标题翻译：高电压GaN晶体管
公开(公告)号：US20110114997A1
公开(公告)日：2011-05-19
申请号：US13014619
申请日：2011-01-26
申请人： YIFENG WU , Primit Parikh , Umesh Mishra
发明人： YIFENG WU , Primit Parikh , Umesh Mishra
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/66462 , H01L29/7786
摘要： A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 mΩ-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 mΩ-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.6 mΩ-cm2, or a blocking voltage of at least 900 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 7.0 mΩ-cm2.
摘要翻译：多场板晶体管包括有源区，源极，漏极和栅极。第一间隔层在源极和栅极之间的有源区上方，并且在漏极和栅极之间的有源区上方具有第二间隔层。第一间隔层上的第一场板连接到栅极。第二间隔层上的第二场板连接到栅极。第三间隔层位于第一间隔层，第二间隔层，第一场板，栅极和第二场板上，在第三间隔层上具有第三场板并连接到源极。晶体管表现出至少600伏特的阻断电压，同时支持至少2安培的电流，其导通电阻不超过5.0mΩ（OHgr·-cm2）为至少600伏，同时支持至少3安培的电流耐电压不超过5.3mΩ，OHgr--cm2，至少900V，同时支持至少2安培的电流，导通电阻不超过6.6mΩ，OHgr-cm2，或阻断电压至少为900V，同时支持至少3安培的电流，导通电阻不超过7.0mΩ，OHgr; -cm2。

5. 发明申请

US20100140660A1 Semiconductor Heterostructure Diodes 有权
标题翻译：半导体异质结二极管
公开(公告)号：US20100140660A1
公开(公告)日：2010-06-10
申请号：US12332284
申请日：2008-12-10
申请人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
发明人： Yifeng Wu , Umesh Mishra , Primit Parikh , Rongming Chu , Ilan Ben-Yaacov , Likun Shen
IPC分类号： H01L29/872
CPC分类号： H01L29/0615 , H01L27/0629 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/872
摘要： Planar Schottky diodes for which the semiconductor material includes a heterojunction which induces a 2DEG in at least one of the semiconductor layers. A metal anode contact is on top of the upper semiconductor layer and forms a Schottky contact with that layer. A metal cathode contact is connected to the 2DEG, forming an ohmic contact with the layer containing the 2DEG.
摘要翻译：平面肖特基二极管，其半导体材料包括在至少一个半导体层中诱导2DEG的异质结。金属阳极触点位于上半导体层的顶部，与该层形成肖特基接触。金属阴极接触件连接到2DEG，与包含2DEG的层形成欧姆接触。

6. 发明申请

US20090236635A1 WIDE BANDGAP HEMTS WITH SOURCE CONNECTED FIELD PLATES 有权
标题翻译：具有源连接的现场板的宽带带
公开(公告)号：US20090236635A1
公开(公告)日：2009-09-24
申请号：US12437505
申请日：2009-05-07
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L29/778 , H01L29/80
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/41725 , H01L29/42316 , H01L29/7787
摘要： A HEMT comprising an active region comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the active region. A spacer layer is formed on at least a portion of a surface of said active region and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.
摘要翻译：一种HEMT，其包括有源区，该有源区包括在基板上形成的多个有源半导体层。源电极，漏电极和栅极形成为与有源区电接触。间隔层形成在所述有源区域的表面的至少一部分上并覆盖栅极。在间隔层上形成场板，并与源电极电连接，其中场板减小HEMT中的峰值工作电场。

7. 发明授权

US07550783B2 Wide bandgap HEMTs with source connected field plates 有权
标题翻译：宽带隙HEMT与源连接的现场板
公开(公告)号：US07550783B2
公开(公告)日：2009-06-23
申请号：US10958970
申请日：2004-10-04
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L29/778
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/41725 , H01L29/42316 , H01L29/7787
摘要： A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.
摘要翻译：一种HEMT，其包括在基板上形成的多个有源半导体层。源电极，漏电极和栅极形成为与多个有源层电接触。间隔层形成在所述多个有源层的表面的至少一部分上并覆盖栅极。在间隔层上形成场板，并与源电极电连接，其中场板减小HEMT中的峰值工作电场。

8. 发明授权

US07476956B2 Gallium nitride based diodes with low forward voltage and low reverse current operation 有权
标题翻译：具有低正向电压和低反向电流操作的氮化镓基二极管
公开(公告)号：US07476956B2
公开(公告)日：2009-01-13
申请号：US10445130
申请日：2003-05-20
申请人： Primit Parikh , Umesh Mishra
发明人： Primit Parikh , Umesh Mishra
IPC分类号： H01L27/095 , H01L29/812 , H01L31/108
CPC分类号： H01L29/475 , H01L29/2003 , H01L29/872 , H01L29/88
摘要： New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.
摘要翻译：公开了具有低导通状态电压（Vf）和保持反向电流（Irev）相对较低的结构的新的基于III族的二极管。本发明的一个实施例是由GaN材料系统制成的肖特基势垒二极管，其中费米能级（或表面电位）不被固定。金属对半导体结的势垒电位根据所使用的金属类型而变化，并且使用特定的金属降低二极管的肖特基势垒电位，并导致Vf在0.1-0.3V的范围内。在另一个实施例中，在肖特基二极管半导体材料上形成沟槽结构以减少反向漏电流。并且包括多个平行的等间距的沟槽，其间具有相邻沟槽之间的台面区域。本发明的第三实施例提供了一种具有低Vf的GaN隧道二极管，其由电子穿过势垒电位而不是在其上引起。该实施例还可以具有沟槽结构以减少反向漏电流。

9. 发明授权

US07388236B2 High efficiency and/or high power density wide bandgap transistors 有权
标题翻译：高效率和/或高功率密度宽带隙晶体管
公开(公告)号：US07388236B2
公开(公告)日：2008-06-17
申请号：US11392114
申请日：2006-03-29
申请人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
发明人： Yifeng Wu , Primit Parikh , Umesh Mishra , Marcia Moore
IPC分类号： H01L29/43
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/404 , H01L29/42316
摘要： Field effect transistors having a power density of greater than 40 W/mm when operated at a frequency of at least 4 GHz are provided. The power density of at least 40 W/mm may be provided at a drain voltage of 135 V. Transistors with greater than 60% PAE and a power density of at least 5 W/mm when operated at 10 GHz at drain biases from 28 V to 48 V are also provided.
摘要翻译：提供了以至少4GHz的频率工作时功率密度大于40W / mm的场效应晶体管。在135V的漏极电压下可以提供至少40W / mm的功率密度。当在10GHz下工作时，具有大于60％PAE的功率密度至少为5W / mm的功率密度，漏极偏压为28V 至48 V。

10. 发明授权

US07126426B2 Cascode amplifier structures including wide bandgap field effect transistor with field plates 有权
标题翻译：串行放大器结构，包括具有场板的宽带隙场效应晶体管
公开(公告)号：US07126426B2
公开(公告)日：2006-10-24
申请号：US10856098
申请日：2004-05-28
申请人： Umesh Mishra , Primit Parikh , Yifeng Wu
发明人： Umesh Mishra , Primit Parikh , Yifeng Wu
IPC分类号： H03F3/14 , H03F1/22
CPC分类号： H01L29/402 , H01L27/0605 , H01L29/1608 , H01L29/2003 , H01L29/42316 , H01L29/7787 , H01L29/812
摘要： A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.
摘要翻译：多级放大器电路被布置成在放大信号时利用非场板和场板晶体管的期望特性。根据本发明的多级放大器的一个实施例包括非场板晶体管和场板晶体管。场板晶体管具有至少一个场板，其布置成在操作期间降低场板晶体管内的电场强度。非场板晶体管连接到场板晶体管，非场板提供电流增益，场板晶体管提供电压增益。在一个实施例中，非场板和场板晶体管以共源共栅布置耦合在一起。

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