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1. 发明授权

US5543235A Multiple grade cemented carbide articles and a method of making the same 失效
标题翻译：多级硬质合金制品及其制造方法
公开(公告)号：US5543235A
公开(公告)日：1996-08-06
申请号：US233388
申请日：1994-04-26
申请人： Prakash K. Mirchandani , Robert E. Thomas , Mark Cippel
发明人： Prakash K. Mirchandani , Robert E. Thomas , Mark Cippel
IPC分类号： B22F7/06 , B22F3/12
CPC分类号： B22F7/06 , Y10T428/12021 , Y10T428/12049 , Y10T428/12056 , Y10T428/12063 , Y10T428/12097
摘要： The present invention provides multiple grade, composite cemented carbide articles and a method of making such articles. The cemented carbide articles comprise carbides of different grades (or different compositions and/or microstructures) and, therefore, correspondingly different properties at different locations in the same article. The method of the present invention comprises filling different areas or portions of a die with metallurgical powders having different compositions and/or microstructures. The powder is then compressed as a single compact in the die cavity. The compressed compact is subsequently sintered to produce a multigrade cemented carbide article having composition and/or microstructural variations within the volume of the article.
摘要翻译：本发明提供多级复合硬质合金制品及其制造方法。硬质合金制品包括不同等级（或不同的组成和/或微观结构）的碳化物，因此在相同制品中的不同位置处相应地具有不同的性质。本发明的方法包括用具有不同组成和/或微结构的冶金粉末填充模具的不同区域或部分。然后将粉末作为单个压块压缩在模腔中。压缩的压块随后被烧结以产生在制品的体积内具有组成和/或微结构变化的多层硬质合金制品。

2. 发明授权

US5960215A Transmit data FIFO for flow controlled data 失效
标题翻译：发送流量控制数据的数据FIFO
公开(公告)号：US5960215A
公开(公告)日：1999-09-28
申请号：US712742
申请日：1996-09-12
申请人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Koichi Tanaka
发明人： Robert E. Thomas , Robert J. Simcoe , Peter J. Roman , Koichi Tanaka
IPC分类号： G06F13/12 , H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： H04L47/10 , G06F13/128 , H04L49/309 , H04L49/90 , H04L49/901 , H04L49/9078 , H04Q11/0478 , H04L2012/5652 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer. The data transfer circuitry is prevented from transferring further data from the host memory to the transmit buffer memory storing the controlled data units when it is determined that there is not enough room in the transmit buffer memory storing the controlled data units to accommodate another data unit. The data transfer circuitry is allowed, however, to transfer further data from the host memory to the transmit buffer memory storing the uncontrolled data units.
摘要翻译：一种用于在主机存储器和外围接口之间传送数据单元的方法和装置，所述数据单元经受流量控制机制，由此一些所述数据单元被流控制，并且所述数据单元中的一些不是。两个发送缓冲存储器耦合到外围接口; 一个用于存储要传送到外围接口的受控数据单元，另一个用于存储要传送到外围接口的不受控制的数据单元。单个请求缓冲器将要从主机存储器传送的数据的连续请求存储到两个发送缓冲存储器中的任一个。数据传输电路响应于存储在请求缓冲器中的请求，将数据从主机存储器传送到两个发送缓冲存储器中的任一个。当确定存储受控数据单元以容纳另一个数据单元的发送缓冲存储器中没有足够的空间时，防止数据传送电路将另外的数据从主机存储器传送到存储受控数据单元的发送缓冲存储器。然而，允许数据传输电路将另外的数据从主机存储器传送到存储非受控数据单元的发送缓冲存储器。

3. 发明授权

US5867480A Method and apparatus for controlling congestion in a network node 失效
标题翻译：控制网络节点拥塞的方法和装置
公开(公告)号：US5867480A
公开(公告)日：1999-02-02
申请号：US712683
申请日：1996-09-12
申请人： Robert E. Thomas , Koichi Tanaka , Peter J. Roman , Wing Cheung , Shinichi Mizuguchi
发明人： Robert E. Thomas , Koichi Tanaka , Peter J. Roman , Wing Cheung , Shinichi Mizuguchi
IPC分类号： H04L12/56 , G01R31/08 , G06F11/00 , G08C15/00
CPC分类号： H04L12/5602 , H04L2012/5635 , H04L2012/5637 , H04L2012/5679
摘要： In a network node having a host system coupled to a network by an adapter, VC-specific congestion is detected and reported to the host system. The host memory includes rx slots or buffers, each corresponding to one of one or more supported slot types. Per-VC slots consumed counters are maintained to count slot consumption for each active VC. Free buffer FIFOs are maintained for each of the one or more slot types, which have a predetermined congestion threshold associated therewith. Entries in each free buffer FIFO correspond to an rx slot posted by the host system. When a new rx slot or buffer in host memory is to be allocated to an incoming cell received on a given VC, the slots consumed counter is compared to the predetermined congestion threshold. If they are equal, the VC is at threshold level and the incoming cell is discarded and a report is sent to the host system. If the slots consumed counter is below threshold, a new rx slot is allocated for the reception of the data and the slots consumed counter is incremented. If the VC is credit-based flow control enabled and the slots consumed counter is below threshold, a credit is returned. If the VC is credit-based flow control enabled and the slots consumed counter is greater than or equal to the threshold, the credit return is deferred until the counter falls below threshold.
摘要翻译：在具有通过适配器耦合到网络的主机系统的网络节点中，检测到VC特定的拥塞并将其报告给主机系统。主机存储器包括rx时隙或缓冲器，每个对应于一个或多个支持的时隙类型之一。维护每个VC槽消耗的计数器以计算每个活动VC的时隙消耗。对于具有与其相关联的预定拥塞阈值的一个或多个时隙类型中的每一个，维持空闲缓冲器FIFO。每个空闲缓冲区FIFO中的条目对应于由主机系统发布的rx时隙。当将主机存储器中的新的rx时隙或缓冲区分配给在给定VC上接收到的传入小区时，将这些时隙消耗的计数器与预定拥塞阈值进行比较。如果它们相等，则VC处于阈值级别，并且传入的信元被丢弃并且报告被发送到主机系统。如果消耗的时隙计数器低于阈值，则为数据的接收分配一个新的rx时隙，并增加消耗的时隙计数器。如果VC是启用了基于信用的流量控制，并且消耗的消费计数器低于阈值，则返回信用。如果VC是启用了基于信用的流量控制，并且消费的时隙计数器大于或等于该阈值，那么信用回报被推迟到计数器低于阈值。

4. 发明授权

US5862206A Method and apparatus for performing raw cell status report frequency mitigation on transmit in a network node 失效
标题翻译：用于在网络节点中进行发送时执行原始小区状态报告频率减轻的方法和装置
公开(公告)号：US5862206A
公开(公告)日：1999-01-19
申请号：US707894
申请日：1996-09-12
申请人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/26
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5652 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： A status report frequency mitigation mechanism for mitigating the frequency of status report generation for raw cells during transmit operations in a network node is presented. The status report frequency mitigation mechanism operates to adjust the frequency with which status reports for raw cells are generated by manipulating the End-of-Packet (EOP) bit in transmit slot descriptors associated with transmit slots containing raw cell data.
摘要翻译：提出了一种用于在网络节点的发送操作期间减轻原始小区的状态报告生成频率的状态报告频率缓解机制。状态报告频率缓解机制通过操纵与包含原始小区数据的发送时隙相关联的发送时隙描述符中的分组结束（EOP）比特来调整用于生成原始小区的状态报告的频率。

5. 发明授权

US5313641A Fast arbiter having easy scaling for large numbers of requesters, large numbers of resource types with multiple instances of each type, and selectable queing disciplines 失效
标题翻译：快速仲裁器可以方便地为大量的请求者定标，大量的资源类型，每种类型的多个实例，以及可选择的排队规则
公开(公告)号：US5313641A
公开(公告)日：1994-05-17
申请号：US1134
申请日：1993-01-06
申请人： Robert J. Simcoe , Robert E. Thomas
发明人： Robert J. Simcoe , Robert E. Thomas
IPC分类号： G06F13/362 , G06F13/14
CPC分类号： G06F13/362
摘要： An arbitration mechanism for controlling a coupling order between a number of resources and a number of requesters having a number of requests processing units, one associated with each one of the requesters, for receiving a resource type request signal from the associated requester, a number of grant processing units, one associated with each one of the resources, for monitoring a busy status signal from said associated resource, a common broadcast medium coupled to the number of request processing units and the grant processing units, and an arbiter for granting access to said common broadcast medium to one of the request processing units and the grant processing units using the common broadcast medium to control the coupling order between the requesters and the resources in a first come, first served manner.
摘要翻译：一种用于控制多个资源与具有多个请求处理单元的请求者之间的耦合顺序的仲裁机制，一个与请求者中的每一个相关联的请求者，用于从相关联的请求者接收资源类型请求信号，多个授权处理单元，与每个资源相关联的一个，用于监视来自所述相关资源的繁忙状态信号;耦合到所述多个请求处理单元和所述授权处理单元的公共广播媒体;以及仲裁器，用于授予对所述公共广播介质到请求处理单元之一以及使用公共广播介质的授权处理单元，以先到先得的方式控制请求者与资源之间的耦合顺序。

6. 外观设计

USD260661S Backgammon gameboard 失效
公开(公告)号：USD260661S
公开(公告)日：1981-09-08
申请号：US63492
申请日：1979-08-06
申请人： Robert M. Thomas , Robert E. Thomas
设计人： Robert M. Thomas , Robert E. Thomas

7. 发明授权

US4094318A Electronic control means for a plurality of intravenous infusion sets 失效
标题翻译：用于多个静脉输液组的电子控制装置
公开(公告)号：US4094318A
公开(公告)日：1978-06-13
申请号：US703907
申请日：1976-07-09
申请人： George K. Burke , Robert J. LeFevre , Robert E. Thomas
发明人： George K. Burke , Robert J. LeFevre , Robert E. Thomas
IPC分类号： A61M5/00 , A61M5/168 , G05D7/06
CPC分类号： G05D7/0635 , A61M5/1689 , Y10S128/13
摘要： Electronic control apparatus for controlling the administration of a plurality of separate fluids independently and consecutively, includes electrical circuitry connected with a plurality of valve operators to operate valves in a plurality of sets to control flow therethrough.
摘要翻译：独立且连续地控制多个单独流体的管理的电子控制装置包括与多个阀操作器连接的电路，以操作多组中的阀以控制流过其中的流量。

8. 发明授权

US6067563A Method and apparatus for avoiding control reads in a network node 有权
标题翻译：用于避免网络节点中的控制读取的方法和装置
公开(公告)号：US6067563A
公开(公告)日：2000-05-23
申请号：US306588
申请日：1999-05-06
申请人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Douglas M. Washabaugh , Peter J. Roman , Wing Cheung
IPC分类号： G06F11/30 , H04L12/56 , H04L29/06 , H04Q11/04 , G06F13/00
CPC分类号： H04L47/522 , G06F11/3006 , G06F11/3027 , G06F11/3055 , G06F11/3096 , H04L29/06 , H04L47/521 , H04L49/90 , H04L49/901 , H04L49/9036 , H04Q11/0478 , H04L2012/5616 , H04L2012/5635 , H04L2012/5658 , H04L2012/5679 , H04L2012/5681
摘要： A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.
摘要翻译：提出了一种用于避免在系统总线上启动控制读取事务的机制，该系统总线耦合具有主机存储器的主机系统和连接到外围单元的接口，因为数据在主机系统和外围设备之间移动。将与主机存储器中的数据存储器部分相关联的控制信息写入存储输出数据和数据存储器部分的数据存储器部分的接口以接收输入数据。该接口包括控制器，用于通过首先获得相关联的数据部分的控制信息来在主机存储器和接口之间移动数据。该接口通过系统总线写入与接口和主机存储器之间的数据移动相关联的状态报告。因此，该机制使得能够在没有异常条件的情况下通过系统进行数据传输而不启动控制读取。

9. 发明授权

US5970229A Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit buffer memory 失效
标题翻译：用于执行从主机存储器到发送缓冲存储器的数据DMA传输的预先调度的装置和方法
公开(公告)号：US5970229A
公开(公告)日：1999-10-19
申请号：US707896
申请日：1996-09-12
申请人： Robert E. Thomas , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Peter J. Roman , Wing Cheung
IPC分类号： G06F13/38 , G06F13/00
CPC分类号： G06F13/387
摘要： An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter. A data transfer is initiated from the source memory to the transmit buffer memory via the bus when a valid entry is stored at the location in the schedule table pointed to by the schedule table pointer. The data is then transferred out of the transmit buffer memory to the peripheral interface when the current time counter reaches the value representing at least the same point in time that was represented by the schedule table pointer when the data transfer was initiated. Data transfers from the transmit buffer memory are thereby synchronized in time with their corresponding entries in the schedule table.
摘要翻译：用于经由总线将数据从源存储器（例如，主机存储器）传送到外围接口的装置和方法利用耦合到外围接口的发送缓冲存储器和以数据的速率前进的当前时间计数器从发送缓冲存储器传送到外设接口。调度表数据结构存储其部分或全部位置中的条目，其中每个位置对应于将数据从发送缓冲存储器传送到外围接口的时间点。调度表指针用于指向调度表中的连续位置。调度表指针以比当前时间计数器更快的速率前进，使得调度表指针表示在当前时间计数器当前输出的时间点之前的时间点。当有效条目存储在调度表指针指向的调度表中的位置时，通过总线从源存储器发送到发送缓冲存储器的数据传输。然后，当当前时间计数器达到表示数据传输启动时由调度表指针表示的至少相同的时间点的值时，将数据传送到发送缓冲存储器中的外设接口。因此，从发送缓冲存储器的数据传输在时间上与其在调度表中的相应条目同步。

10. 发明授权

US5941952A Apparatus and method for transferring data from a transmit buffer memory at a particular rate 失效
标题翻译：用于以特定速率从发送缓冲存储器传送数据的装置和方法
公开(公告)号：US5941952A
公开(公告)日：1999-08-24
申请号：US712687
申请日：1996-09-12
申请人： Robert E. Thomas , Peter J. Roman , Wing Cheung
发明人： Robert E. Thomas , Peter J. Roman , Wing Cheung
IPC分类号： H04L12/56 , H04Q11/04 , G06F13/38 , G06F15/17
CPC分类号： H04Q11/0478 , H04L2012/5616 , H04L2012/5635 , H04L2012/5658 , H04L2012/5664 , H04L2012/5667 , H04L2012/5679 , H04L2012/5681
摘要： An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory. Circuitry is then operative on each valid entry read from the schedule table to generate a request for a data transfer between the source memory and the transmit buffer memory; perform a data transfer from the source memory to the transmit buffer memory in response to the request; and transfer the data from the transmit buffer memory when the current time circuitry output reaches a value representing at least the same point in time that is represented by the timestamp associated with the entry for which the request was generated.
摘要翻译：一种用于将数据从源存储器传送到发送缓冲存储器然后以特定速率从发送缓冲存储器传送的装置和方法。当前时间计数器以数据从发送缓冲存储器发送到接口的速率前进。调度存储器存储条目，每个有效条目与要从发送缓冲存储器发送到接口的数据相关联。时间戳与调度存储器中的每个有效条目相关联。然后对从调度表读取的每个有效条目进行电路以产生对源存储器和发送缓冲存储器之间的数据传输的请求; 响应于该请求，执行从源存储器到发送缓冲存储器的数据传输; 并且当当前时间电路输出达到表示与由生成请求的条目相关联的时间戳表示的至少相同的时间点的值时，传送来自发送缓冲存储器的数据。

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