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1. 发明申请

US20090114950A1 Semiconductor Device and Method of Manufacturing such a Device 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090114950A1
公开(公告)日：2009-05-07
申请号：US11597533
申请日：2005-05-19
申请人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
发明人： Prabhat Agarwal , Jan Willem Slotboom , Gerben Doornbos
IPC分类号： H01L21/336 , H01L21/8249 , H01L21/8232 , H01L29/78 , H01L29/80 , H01L21/8234 , H01L21/8248
CPC分类号： H01L21/8249
摘要： The invention relates to a semiconductor device (10) comprising a substrate (11) and a semiconductor body (1) of silicon having a semiconductor layer structure comprising, in succession, a first and a second semiconductor layer (2, 3), and having a surface region of a first conductivity type which is provided with a field effect transistor (M) with a channel of a second conductivity type, opposite to the first conductivity type, wherein the surface region is provided with source and drain regions (4A, 4B) of the second conductivity type for the field effect transistor (M) and with—interposed between said source and drain regions—a channel region (3A) with a lower doping concentration which forms part of the second semiconductor layer (3) and with a buried first-conductivity-type semiconductor region (2A), buried below the channel region (3A), with a doping concentration that is much higher than that of the channel region (3A) and which forms part of the first semiconductor layer (2). According to the invention, the semiconductor body (1) is provided not only with the field effect transistor (M) but also with a bipolar transistor (B) with emitter, base and collector regions (5A, 5B, 5C) of respectively the second, the first and the second conductivity type, and the emitter region (5A) is formed in the second semiconductor layer (3) and the base region (5B) is formed in the first semiconductor layer (2). In this way a Bi(C)MOS IC (10) is obtained which is very suitable for high-frequency applications and which is easy to manufacture using a method according to the invention. Preferably the first semiconductor layer (2) comprises Si—Ge and is delta-doped, whereas the second semiconductor layer (3) comprises strained Si.
摘要翻译：本发明涉及一种半导体器件（10），它包括具有半导体层结构的硅衬底（12）和半导体本体（1），半导体层结构依次包括第一和第二半导体层（2,3），并且具有具有与第一导电类型相反的具有第二导电类型的沟道的场效应晶体管（M）的第一导电类型的表面区域，其中所述表面区域设置有源极和漏极区域（4A，4B））和用于场效应晶体管（M）的第二导电类型，并且插入在所述源极和漏极区之间 - 具有较低掺杂浓度的沟道区（3A），其形成第二半导体层（3）的一部分，并且具有埋入第一导电型半导体区域（2A），其掺杂在沟道区域（3A）的下方，掺杂浓度比沟道区域（3A）的掺杂浓度高得多，并且形成第一半导体层（2）的一部分，。根据本发明，半导体本体（1）不仅设置有场效应晶体管（M），而且还具有双极晶体管（B），发射极，基极和集电极区域（5A，5B，5C）分别为第二第一和第二导电类型和发射极区域（5A）形成在第二半导体层（3）中，并且基极区域（5B）形成在第一半导体层（2）中。以这种方式获得了非常适合于高频应用并且易于使用根据本发明的方法制造的Bi（C）MOS IC（10）。优选地，第一半导体层（2）包括Si-Ge并且是δ掺杂的，而第二半导体层（3）包括应变Si。

2. 发明授权

US07671447B2 Bipolar transistor and method of manufacturing the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07671447B2
公开(公告)日：2010-03-02
申请号：US11632614
申请日：2005-07-07
申请人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
发明人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
IPC分类号： H01L23/58
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 1019 and about 1020 at/cm3, and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中，从投影中观察，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有δ形轮廓的高掺杂子区域（2A），并且所述高度掺杂子区域（2A）横向延伸至收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选介于约1019至约1020 at / cm3，子区（2A）的厚度在1至15nm之间，优选在1至10nm之间。本发明还包括制造这种装置（10）的方法。

3. 发明授权

US07989844B2 Semiconductor device and method of manufacturing such a device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07989844B2
公开(公告)日：2011-08-02
申请号：US10545736
申请日：2004-02-12
申请人： Rob Van Dalen , Prabhat Agarwal , Jan Willem Slotboom , Gerrit Elbert Johannes Koops
发明人： Rob Van Dalen , Prabhat Agarwal , Jan Willem Slotboom , Gerrit Elbert Johannes Koops
IPC分类号： H01L29/732 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1). In this way, on the one hand, a low-impedance emitter contact is ensured, while locally the Gummel number is increased without the drawbacks normally associated with such an increase. In this way, the hole current in the, npn, transistor is increased and thus the gain is decreased. The relatively high gain of a Si—Ge transistor is responsible for the low BVCeOf which is consequently avoided in a device (10) according to the invention. Preferably the further semiconductor region (20) is recessed in the emitter region (1) and said emitter region (1) preferably comprises a lower doped part that borders on the base region (2) and that is situated below the further semiconductor region (20). The invention also comprises a method of manufacturing a semiconductor device (10) according to the invention.
摘要翻译：本发明涉及具有衬底（11）和具有异质结双极性的半导体本体（12）的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管），其分别设置有第一，第二和第三连接导体（4,5,6），并且其中所述基极区域（2）的带隙小于所述集电极区域（3）的带隙或的发射极区域（1），例如通过在基极区域（2）中使用硅 - 锗混合晶体代替纯硅。这种器件的特点是非常高的速度，但其晶体管显示相对较低的BVeeo。在根据本发明的器件（10）中，发射极区域（1）的掺杂通量被嵌入在发射极区域（1）中的第二导电类型的另外的半导体区域（20）局部地减小。以这种方式，一方面，确保了低阻抗发射极接触，而局部地增加了Gummel数量，而没有通常与这种增加相关联的缺点。以这种方式，npn晶体管中的空穴电流增加，因此增益降低。 Si-Ge晶体管的相对高的增益负责在本发明的器件（10）中避免的低BVCeOf。优选地，另外的半导体区域（20）凹陷在发射极区域（1）中，并且所述发射极区域（1）优选地包括在基极区域（2）上接合并位于另外的半导体区域（20）下方的下部掺杂部分）。本发明还包括制造根据本发明的半导体器件（10）的方法。

4. 发明申请

US20080083968A1 Bipolar Transistor And Method Of Manufacturing The Same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US20080083968A1
公开(公告)日：2008-04-10
申请号：US11632614
申请日：2005-07-07
申请人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
发明人： Andreas Hubertus Montree , Jan Willem Slotboom , Prabhat Agarwal , Philippe Meunier-Beillard
IPC分类号： H01L27/082 , H01L21/328
CPC分类号： H01L29/7317 , H01L29/1004 , H01L29/365 , H01L29/66265 , H01L29/735 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications. The doping concentration lies preferably between about 1019 and about 1020 at/cm3, and the thickness of the sub-region (2A) lies between 1 and 15 nm and preferably between 1 and 10 nm. The invention also comprises a method of manufacturing such a device (10).
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区域（1），基极区域（2）和集电极区域（3），与第一导电类型相反的第二导电类型和第一导电类型，其中从投影中看，发射极区域（1）位于基极区域（2）的上方或下方，并且集电极区域（3）横向地邻接基部区域（2）。根据本发明，基极区域（2）包括其掺杂浓度在厚度方向上具有Δ形轮廓的高掺杂子区域（2A），并且所述高掺杂子区域（2A）横向延伸为作为收集器区域（3）。这种横向双极晶体管在基极和集电极区域（2,3）之间具有优异的高频特性和较高的击穿电压，这意味着该器件适用于高功率应用。掺杂浓度优选在/ cm 3和约10 20之间，并且子区域（2A）的厚度）位于1至15nm之间，优选在1至10nm之间。本发明还包括制造这种装置（10）的方法。

5. 发明申请

US20120038002A1 IC AND IC MANUFACTURING METHOD 有权
标题翻译： IC和IC制造方法
公开(公告)号：US20120038002A1
公开(公告)日：2012-02-16
申请号：US13148023
申请日：2010-01-15
申请人： Tony Vanhoucke , Anco Heringa , Johannes Josephus Theodorus Martinus Donkers , Jan Willem Slotboom
发明人： Tony Vanhoucke , Anco Heringa , Johannes Josephus Theodorus Martinus Donkers , Jan Willem Slotboom
IPC分类号： H01L27/06 , H01L21/8249
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/7322
摘要： Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.
摘要翻译：公开了一种在CMOS工艺中制造垂直双极晶体管的方法，包括将第一类型的杂质注入到衬底（100）中以在其中形成掩埋区域（150,260）; 使用第二类型的杂质和使用第一类型的杂质的浅植入物（132）形成晕轮植入物（134），所述晕轮植入物将衬底中的浅植入物包围并位于所述掩埋区域（150,250））; 与所述晕轮植入物（134）相邻地形成使用所述第二类型的杂质的另外的植入物（136），用于提供与所述晕轮植入物的导电连接; 以及向所述另外的植入物（136）提供相应的连接（170,160,270），所述浅植入物（132）和所述掩埋区域（150,260）允许所述浅植入物，晕圈植入物和掩埋区域分别可作为发射体，垂直双极晶体管的基极和集电极。因此，可以提供包括仅使用CMOS处理步骤制造的垂直双极晶体管的IC。

6. 发明授权

US06593628B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06593628B2
公开(公告)日：2003-07-15
申请号：US09819280
申请日：2001-03-28
申请人： Ronald Dekker , Henricus Godefridus Rafael Maas , Jan Willem Slotboom , Freerk Van Rijs
发明人： Ronald Dekker , Henricus Godefridus Rafael Maas , Jan Willem Slotboom , Freerk Van Rijs
IPC分类号： H01L2701
CPC分类号： H01L27/0825 , H01L21/8222 , H01L21/84 , H01L27/088 , H01L27/1203
摘要： The invention relates to an essentially discrete semiconductor device comprising a semiconductor body (10) having a first, preferably bipolar, transistor (T1) with a first region (1) forming a collector (1) of T1, and a second, preferably also bipolar, transistor (T2) with a second region (2) forming a collector (2) of T2, which transistors (T1, T2) are in a cascode configuration wherein the collector (1) of T1is connected to the emitter (4) of T2. Such a device cannot suitably be used in a base station for mobile communication. According to the invention, the first region (1) and the second region (2) are positioned next to each other within a semiconductor region (5), a part of which situated below the first region (1) is provided with a higher doping concentration at the location of T1. In this way, T1 has a low collector-emitter breakdown voltage and a high cutoff frequency, whereas for T2 said voltage and frequency are, respectively, high(er) and low(er). The resultant device is very suitable, on the one hand, for a high voltage application, for example 28 V, and a high power application, for example 100 W and, on the other hand, the device can still operate at a very high speed and hence is very suitable for the above application. Moreover, the device can be manufactured very easily using a method according to the invention. Preferably, the device is rendered suitable for surface mounting, and the semiconductor body is attached to an isolating substrate (20), while the parts thereof that are situated outside T1 and T2 are removed.
摘要翻译：本发明涉及一种基本上分立的半导体器件，其包括具有第一优选为双极晶体管（T1）的半导体本体（10），其中第一区域（1）形成为T1的集电极（1），第二区域（1）优选为双极晶体管，具有形成T2的集电极（2）的第二区域（2）的晶体管（T2），所述晶体管（T1，T2）处于共源共栅结构，其中T1的集电极（1）连接到T2的发射极（4）。这样的设备不能适用于用于移动通信的基站。根据本发明，第一区域（1）和第二区域（2）在半导体区域（5）内彼此相邻定位，其一部分位于第一区域（1）的下方，具有较高的掺杂集中在T1的位置。以这种方式，T1具有低集电极 - 发射极击穿电压和高截止频率，而对于T2，所述电压和频率分别为高（呃）和低（呃）。一方面，所得到的装置非常适合于高压应用，例如28V，以及高功率应用，例如100W，另一方面，该装置仍然可以以非常高的速度运行因此非常适合于上述应用。此外，可以使用根据本发明的方法非常容易地制造该装置。优选地，该装置适于表面安装，并且半导体主体附接到隔离衬底（20），而位于T1和T2外部的部分被去除。

7. 发明授权

US07109567B2 Semiconductor device and method of manufacturing such device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07109567B2
公开(公告)日：2006-09-19
申请号：US10495943
申请日：2002-11-21
申请人： Raymond Josephus Engelbart Hueting , Jan Willem Slotboom , Leon Cornelis Maria Van Den Oever
发明人： Raymond Josephus Engelbart Hueting , Jan Willem Slotboom , Leon Cornelis Maria Van Den Oever
IPC分类号： H01L27/082 , H01L21/8238
CPC分类号： H01L29/47 , H01L29/41708 , H01L29/42304 , H01L29/7378
摘要： The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a third connection conductor (4, 5, 6), while the bandgap of the base region (2) is lower than that of the collector region (3) or of the emitter region (1), for example owing to the use of a silicon-germanium alloy instead of pure silicon. Such a device is very fast, but its transistor shows a relatively low BVceo. In a device according to the invention, the emitter region (1) or the base region (2) comprises a sub-region (1B, 2B) with a reduced doping concentration, which sub-region (1B, 2B) is provided with a further connection conductor (4B, 5B) which forms a Schottky junction with the sub-region (1B, 2B). Such a device results in a transistor with a particularly high cut-off frequency fT but with no or hardly any reduction of the BVceo. In a preferred embodiment, the emitter region (1) and its sub-region (1B), or the base region (2) and its sub-region (2B) both border the surface of the semiconductor body (10) and the further connection conductor (4B, 5B) forms part of the first or the second connection conductor (4, 5), as applicable. The invention also comprises a method of manufacturing a device according to the invention.
摘要翻译：本发明涉及具有异质结双极的半导体器件，特别是具有发射极区域（1），基极区域（2）和集电极区域（3）的npn晶体管，它们分别设置有第一，第二和第三连接导体（4,5,6），而基极区域（2）的带隙比集电极区域（3）或发射极区域（1）的带隙低，例如由于使用的硅 - 锗合金代替纯硅。这样的器件非常快，但其晶体管显示出相对较低的BVceo。在根据本发明的装置中，发射极区域（1）或基极区域（2）包括具有降低的掺杂浓度的子区域（1B，2B），该子区域（1B，2B）设置有与子区域（1B，2B）形成肖特基结的另外的连接导体（4B，5B）。这种器件导致具有特别高的截止频率fT的晶体管，但是没有或几乎不减少BVceo。在优选实施例中，发射极区域（1）及其子区域（1B）或基极区域（2）及其子区域（2B）都与半导体本体（10）的表面和如果适用，另外的连接导体（4B，5B）形成第一或第二连接导体（4,5）的一部分。本发明还包括一种制造根据本发明的装置的方法。

8. 发明授权

US06410395B1 Method of manufacturing a semiconductor device comprising SiGe HBTs 失效
标题翻译：制造包含SiGe HBT的半导体器件的方法
公开(公告)号：US06410395B1
公开(公告)日：2002-06-25
申请号：US09713865
申请日：2000-11-16
申请人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
发明人： Doede Terpstra , Jan Willem Slotboom , Youri Ponomarev , Petrus Hubertus Cornelis Magnee , Freerk Van Rijs
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L27/0826
摘要： A method of manufacturing a semiconductor device comprising heterojunction bipolar transistors (HBTs), in which method a first semiconductor layer of monocrystalline silicon (5), a second semiconductor layer of monocrystalline silicon comprising 5 to 25 at. % germanium (6) and a third semiconductor layer of monocrystalline silicon (7) are successively provided on a surface (2) of a silicon wafer (1) by means of epitaxial deposition. Base zones of the transistors are formed in the second semiconductor layer. In this method, the second semiconductor layer is deposited without a base doping, said doping being formed at a later stage. Said doping can be formed by means of an ion implantation process or a VPD (Vapor Phase Doping) process. This method enables integrated circuits comprising npn-transistors as well as pnp-transistors to be manufactured.
摘要翻译：一种制造包括异质结双极晶体管（HBT）的半导体器件的方法，其中单晶硅的第一半导体层（5），第二半导体单晶硅的半导体层，包括5至25μm。通过外延沉积，在硅晶片（1）的表面（2）上依次提供了锗（6）和单晶硅（7）的第三半导体层。在第二半导体层中形成晶体管的基极区。在该方法中，第二半导体层被沉积而不进行基底掺杂，所述掺杂在稍后阶段形成。所述掺杂可以通过离子注入工艺或VPD（气相掺杂）工艺形成。该方法使得能够制造包括npn晶体管的集成电路以及pnp晶体管。

9. 发明授权

US09443773B2 IC and IC manufacturing method 有权
标题翻译： IC和IC制造方法
公开(公告)号：US09443773B2
公开(公告)日：2016-09-13
申请号：US13148023
申请日：2010-01-15
申请人： Tony Vanhoucke , Anco Heringa , Johannes Josephus Theodorus Martinus Donkers , Jan Willem Slotboom
发明人： Tony Vanhoucke , Anco Heringa , Johannes Josephus Theodorus Martinus Donkers , Jan Willem Slotboom
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/08 , H01L29/732
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/7322
摘要： Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate (100) to form a buried region (150, 260) therein; forming a halo implant (134) using an impurity of a second type and a shallow implant (132) using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (150, 250); forming, adjacent to the halo implant (134), a further implant (136) using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections (170, 160, 270) to the further implant (136), the shallow implant (132) and the buried region (150, 260) allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.
摘要翻译：公开了一种在CMOS工艺中制造垂直双极晶体管的方法，包括将第一类型的杂质注入到衬底（100）中以在其中形成掩埋区域（150,260）; 使用第二类型的杂质和使用第一类型的杂质的浅植入物（132）形成晕轮植入物（134），所述晕轮植入物将衬底中的浅植入物包围并位于所述掩埋区域（150,250））; 与所述晕轮植入物（134）相邻地形成使用所述第二类型的杂质的另外的植入物（136），用于提供与所述晕轮植入物的导电连接; 以及向所述另外的植入物（136）提供相应的连接（170,160,270），所述浅植入物（132）和所述掩埋区域（150,260）允许所述浅植入物，晕圈植入物和掩埋区域分别可作为发射体，垂直双极晶体管的基极和集电极。因此，可以提供包括仅使用CMOS处理步骤制造的垂直双极晶体管的IC。

10. 发明授权

US07352042B2 Radiation-emitting semiconductor device and method of manufacturing such a device 失效
标题翻译：辐射发射半导体器件及其制造方法
公开(公告)号：US07352042B2
公开(公告)日：2008-04-01
申请号：US10535483
申请日：2003-10-28
申请人： Johan Hendrik Klootwijk , Jan Willem Slotboom
发明人： Johan Hendrik Klootwijk , Jan Willem Slotboom
IPC分类号： H01L27/14
CPC分类号： H01L29/7313 , H01L33/0004
摘要： The invention relates to a radiation-emitting semiconductor device (10) with a semiconductor body (1) and a substrate (2), wherein the semiconductor body (1) comprises a vertical bipolar transistor with an emitter region (3), a base region (4) and a collector region (5), which regions are each provided with a connection region (6, 7, 8), and the border between the base region (4) and the collector region (5) forms a pn-junction and, in operation, at a reverse bias of the pn-junction or at a sufficiently large collector current, avalanche multiplication of charge carriers occurs whereby radiation is generated in the collector region (5). According to the invention, the collector region (5) has a thickness through which transmission of the generated radiation occurs, and the collector region (5) borders on a free surface of the semiconductor body (1).
摘要翻译：本发明涉及具有半导体本体（1）和衬底（2）的辐射发射半导体器件（10），其中半导体本体（1）包括具有发射极区域（3）的垂直双极晶体管，基极区域（4）和集电极区域（5），这些区域各自设置有连接区域（6,7,8），并且基极区域（4）和集电极区域（5）之间的边界形成pn结并且在操作中，在pn结的反向偏压或集电极电流充足的情况下，发生电荷载流子的雪崩倍增，从而在集电极区域（5）中产生辐射。根据本发明，集电区（5）具有产生辐射的透射的厚度，并且集电区（5）与半导体本体（1）的自由表面接合。

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