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1. 发明申请

US20070139081A1 Address transition detector for fast flash memory device 失效
公开(公告)号：US20070139081A1
公开(公告)日：2007-06-21
申请号：US11303863
申请日：2005-12-16
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.

2. 发明授权

US07554860B1 Nonvolatile memory integrated circuit having assembly buffer and bit-line driver, and method of operation thereof 有权
标题翻译：具有组装缓冲器和位线驱动器的非易失性存储器集成电路及其操作方法
公开(公告)号：US07554860B1
公开(公告)日：2009-06-30
申请号：US11859073
申请日：2007-09-21
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： G11C7/10
CPC分类号： G11C7/12 , G11C7/08 , G11C7/1048 , G11C16/24
摘要： An assembly buffer and bitline driver circuit has two inverters cross-coupled to form an assembly buffer. A high-voltage latch is formed from cross-coupled high-voltage inverters. A first low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the first high-voltage inverter and a second low-voltage n-channel MOS transistors is coupled to the high-voltage latch to selectively ground the output of the other high-voltage inverter. The gate of the first low-voltage n-channel MOS transistor is coupled to one output of one of the inverters forming the assembly buffer latch and the gate of the second low-voltage n-channel MOS transistor is coupled to the output of the other one of the inverters forming the assembly buffer latch. A pre-load circuit is used to prevent data in an unselected circuit from being disturbed.
摘要翻译：组装缓冲器和位线驱动器电路具有交叉耦合的两个逆变器以形成组装缓冲器。高压锁存器由交叉耦合的高压逆变器形成。第一低电压n沟道MOS晶体管耦合到高电压锁存器，以选择性地接地第一高压逆变器的输出，而第二低电压n沟道MOS晶体管耦合到高电压锁存器选择性地接地另一个高压逆变器的输出。第一低电压n沟道MOS晶体管的栅极耦合到形成组装缓冲器锁存器的一个反相器的一个输出端，第二低压n沟道MOS晶体管的栅极耦合到另一个的沟道的输出端其中一个逆变器形成组装缓冲器锁存器。使用预加载电路来防止未选择电路中的数据被干扰。

3. 发明申请

US20080036499A1 ADDRESS TRANSITION DETECTOR FOR FAST FLASH MEMORY DEVICE 有权
标题翻译：用于快速闪存存储器的地址转换检测器
公开(公告)号：US20080036499A1
公开(公告)日：2008-02-14
申请号：US11833833
申请日：2007-08-03
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
摘要翻译：地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点和P SUB偏置和N SUB偏置节点。第一到第五级联反相器各自由p沟道和n沟道MOS偏置晶体管供电，其栅极分别耦合到P偏置偏压节点和N SUB偏置节点。第一反相器的输入耦合到输入节点。第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

4. 发明授权

US07532035B2 Address transition detector for fast flash memory device 有权
标题翻译：用于快速闪存器件的地址转换检测器
公开(公告)号：US07532035B2
公开(公告)日：2009-05-12
申请号：US11833833
申请日：2007-08-03
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
摘要翻译：地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点以及Pbias和Nbias节点。第一到第五级联逆变器分别由其通道分别耦合到Pbias节点和Nbias节点的p沟道和n沟道MOS偏置晶体管供电。第一反相器的输入耦合到输入节点。第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

5. 发明授权

US07268589B2 Address transition detector for fast flash memory device 失效
标题翻译：用于快速闪存器件的地址转换检测器
公开(公告)号：US07268589B2
公开(公告)日：2007-09-11
申请号：US11303863
申请日：2005-12-16
申请人： Poongyeub Lee , Ming-Chi Liu
发明人： Poongyeub Lee , Ming-Chi Liu
IPC分类号： H03K19/00
CPC分类号： G11C7/22 , G11C7/04 , G11C7/08 , G11C7/12 , G11C8/18 , G11C2207/061 , G11C2207/2281 , H03K2005/00039
摘要： An address transition detector circuit includes an input node, an output node, a bandgap reference node, and Pbias and Nbias nodes having voltages derived from the bandgap reference node. First through fifth cascaded inverters are each powered by a p-channel and n-channel MOS bias transistors having their gates coupled respectively to the Pbias node and the Nbias node. The input of the first inverter is coupled to the input node. First and second capacitors are coupled respectively to ground from the outputs of the first and fourth cascaded inverters. A NAND gate has a first input coupled to the input node, a second input coupled the output of the fifth cascaded inverter, and an output coupled to the output node.
摘要翻译：地址转换检测器电路包括具有从带隙参考节点导出的电压的输入节点，输出节点，带隙参考节点和P SUB偏置和N SUB偏置节点。第一到第五级联反相器各自由p沟道和n沟道MOS偏置晶体管供电，其栅极分别耦合到P偏置偏压节点和N SUB偏置节点。第一反相器的输入耦合到输入节点。第一和第二电容器从第一和第四级联逆变器的输出分别耦合到地。 NAND门具有耦合到输入节点的第一输入，耦合第五级联反相器的输出的第二输入和耦合到输出节点的输出。

6. 发明授权

US07342832B2 Bit line pre-settlement circuit and method for flash memory sensing scheme 有权
标题翻译：闪存感测方案的位线预结算电路和方法
公开(公告)号：US07342832B2
公开(公告)日：2008-03-11
申请号：US11281253
申请日：2005-11-16
申请人： Poongyeub Lee , MingChi Mitch Liu
发明人： Poongyeub Lee , MingChi Mitch Liu
IPC分类号： G11C16/02 , G11C16/28 , G11C16/24 , G11C7/12 , G11C7/14
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C16/24 , G11C2207/12
摘要： A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.
摘要翻译：闪存阵列包括施加参考电流的参考位线。在读取操作期间，选择用于读取的位线被连接到电流 - 电压转换器，每个转换器基于在位线中流动的输入电流产生输出电压。将电流 - 电压转换器的输出电压与从参考电流 - 电压转换器的输出导出的参考电压进行比较，其参考电压 - 电压转换器的输入由基准位线上的参考电流驱动。任何传导比参考电流更多电流的单元将被视为已擦除单元。相反，传导比参考电流更小电流的任何单元将被视为编程单元。

7. 发明申请

US20080144393A1 BIT LINE PRE-SETTLEMENT CIRCUIT AND METHOD FOR FLASH MEMORY SENSING SCHEME 审中-公开
标题翻译：用于闪存存储器感测方案的位线预解决电路和方法
公开(公告)号：US20080144393A1
公开(公告)日：2008-06-19
申请号：US12037839
申请日：2008-02-26
申请人： Poongyeub Lee , MingChi Mitch Liu
发明人： Poongyeub Lee , MingChi Mitch Liu
IPC分类号： G11C16/24
CPC分类号： G11C16/28 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C16/24 , G11C2207/12
摘要： A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.
摘要翻译：闪存阵列包括施加参考电流的参考位线。在读取操作期间，选择用于读取的位线被连接到电流 - 电压转换器，每个转换器基于在位线中流动的输入电流产生输出电压。将电流 - 电压转换器的输出电压与从参考电流 - 电压转换器的输出导出的参考电压进行比较，其参考电压 - 电压转换器的输入由基准位线上的参考电流驱动。任何传导比参考电流更多电流的单元将被视为已擦除单元。相反，传导比参考电流更小电流的任何单元将被视为编程单元。

8. 发明授权

US06768671B1 Nonvolatile memory and method of operation thereof to control erase disturb 有权
标题翻译：非易失性存储器及其操作方法来控制擦除干扰
公开(公告)号：US06768671B1
公开(公告)日：2004-07-27
申请号：US10382719
申请日：2003-03-05
申请人： Poongyeub Lee , Joo Weon Park , Kwangho Kim , Eungjoon Park
发明人： Poongyeub Lee , Joo Weon Park , Kwangho Kim , Eungjoon Park
IPC分类号： G11C1616
CPC分类号： G11C16/08 , G11C16/12 , G11C16/3418
摘要： In an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.
摘要翻译：在非易失性存储器单元的阵列中，根据需要，甚至整个存储单元阵列可以将多个存储器单元放置在大块的单个区域中，示例性地为p阱。外设电路用于将存储器阵列有效地划分为块和块组，并且在页或块擦除操作期间在这些块和组内建立合适的偏置和反偏置以限制擦除干扰。每个组都有自己的一组电压开关，它们为各种工作模式（包括擦除）提供偏置电压。每个电压开关在选择组时提供大的正电压，或者当其组被选择时提供大的负电压。该组的尺寸被确定为电压开关所需的擦除干扰程度和衬底面积之间的折衷。

9. 发明授权

US06775184B1 Nonvolatile memory integrated circuit having volatile utility and buffer memories, and method of operation thereof 有权
标题翻译：具有易用性和缓冲存储器的非易失性存储器集成电路及其操作方法
公开(公告)号：US06775184B1
公开(公告)日：2004-08-10
申请号：US10349384
申请日：2003-01-21
申请人： Joo Weon Park , Poongyeub Lee
发明人： Joo Weon Park , Poongyeub Lee
IPC分类号： G11C1400
CPC分类号： G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2216/14
摘要： A memory integrated circuit includes a nonvolatile memory array that is programmed in page mode. A volatile utility memory is connected to the memory array, and is at least a page in size so that an entire page of data that is either being programmed into or read from the memory array may be stored in the utility memory, thereby providing a single readily accessible and fully functional volatile memory that supports a variety of data operations such as nonvolatile memory programming, program-verify when supplemented with a program verify detector, data compare when supplemented with a comparator, and other operations including, in particular, operations that can benefit from the availability of a fast volatile memory to store an entire page of program data or read data. The outputs of the program verify detector, the comparator, and potentially the other operations circuits are furnished to a memory control circuit for controlling the memory or setting particular register values, or may be furnished as output through an I/O circuit that implements data input/output functions and performs various data routing and buffering functions for the integrated circuit memory.
摘要翻译：存储器集成电路包括以页模式编程的非易失性存储器阵列。易失性效用存储器连接到存储器阵列，并且至少是一个页面大小，使得正在被编程到存储器阵列中或从存储器阵列读取的整个数据页可以存储在效用存储器中，从而提供单个易于访问和全功能的易失性存储器，其支持各种数据操作，例如非易失性存储器编程，补充有程序验证检测器时的程序验证，补充比较器时的数据比较，以及其他操作，特别是可以受益于快速易失性存储器的可用性，以存储整个程序数据页面或读取数据。程序验证检测器，比较器和潜在的其他操作电路的输出被提供给用于控制存储器或设置特定寄存器值的存储器控制电路，或者可以通过实现数据输入的I / O电路作为输出 /输出功能，并为集成电路存储器执行各种数据路由和缓冲功能。

10. 发明授权

US06909639B2 Nonvolatile memory having bit line discharge, and method of operation thereof 有权
标题翻译：具有位线放电的非易失性存储器及其操作方法
公开(公告)号：US06909639B2
公开(公告)日：2005-06-21
申请号：US10421458
申请日：2003-04-22
申请人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
发明人： Joo Weon Park , Poongyeub Lee , Eungjoon Park , Kyung Joon Han
IPC分类号： G11C11/34 , G11C16/00 , G11C16/04 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , G11C16/10 , H01L27/115 , H01L29/7885
摘要： The problem of bit disturb is reduced by discharging the floating bit lines of a nonvolatile memory array during programming. An illustrative virtual ground memory array uses single transistor floating gate type memory cells that are programmed using Fowler-Nordheim (“FN”) tunneling, highly conductive and lengthy bit lines, buried and relatively short sub-bit lines and a programming discharge circuit for controlling spurious voltages on the bit lines that can arise when some of the bit lines are left floating during programming. Discharge control transistor respectively coupled to the bit lines direct current into a discharge section. A discharge section may be provided for each bit line, or shared by all bit lines. The discharge section may be a fixed circuit section for use through the programming process or may be selected from multiple discharge options.
摘要翻译：通过在编程期间放电非易失性存储器阵列的浮置位线来减少位干扰的问题。示例性虚拟接地存储器阵列使用使用Fowler-Nordheim（“FN”）隧道，高导电性和长度位线，埋入和相对短的子位线以及用于控制的编程放电电路来编程的单晶体管浮栅型存储器单元当编程中某些位线悬空时，位线上的杂散电压可能会出现。分别与位线耦合的放电控制晶体管将电流引入放电部分。可以为每个位线提供放电部分，或者由所有位线共享放电部分。放电部分可以是通过编程处理使用的固定电路部分，或者可以从多个放电选项中选择。

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