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1. 发明授权

US08765588B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08765588B2
公开(公告)日：2014-07-01
申请号：US13248011
申请日：2011-09-28
申请人： Pong-Wey Huang , Chan-Lon Yang , Chang-Hung Kung , Wei-Hsin Liu , Ya-Hsueh Hsieh , Bor-Shyang Liao , Teng-Chun Hsuan , Chun-Yao Yang
发明人： Pong-Wey Huang , Chan-Lon Yang , Chang-Hung Kung , Wei-Hsin Liu , Ya-Hsueh Hsieh , Bor-Shyang Liao , Teng-Chun Hsuan , Chun-Yao Yang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/66545
摘要： A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.
摘要翻译：半导体工艺包括以下步骤。介电层形成在基板上，并且介电层具有第一凹槽和第二凹槽。形成金属层以覆盖介电层的表面，第一凹部和第二凹部。部分地将牺牲的材料填充到第一凹部和第二凹部中，使得每个凹部中的金属层的一部分分别被覆盖。去除每个凹部中的未覆盖的金属层。牺牲的材料被去除。执行蚀刻处理以去除第一凹部中的剩余金属层并且将剩余的金属层保留在第二凹部中。

2. 发明申请

US20130078792A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20130078792A1
公开(公告)日：2013-03-28
申请号：US13248011
申请日：2011-09-28
申请人： Pong-Wey Huang , Chan-Lon Yang , Chang-Hung Kung , Wei-Hsin Liu , Ya-Hsueh Hsieh , Bor-Shyang Liao , Teng-Chun Hsuan , Chun-Yao Yang
发明人： Pong-Wey Huang , Chan-Lon Yang , Chang-Hung Kung , Wei-Hsin Liu , Ya-Hsueh Hsieh , Bor-Shyang Liao , Teng-Chun Hsuan , Chun-Yao Yang
IPC分类号： H01L21/28
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/513 , H01L29/66545
摘要： A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.
摘要翻译：半导体工艺包括以下步骤。介电层形成在基板上，并且介电层具有第一凹槽和第二凹槽。形成金属层以覆盖介电层的表面，第一凹部和第二凹部。部分地将牺牲的材料填充到第一凹部和第二凹部中，使得每个凹部中的金属层的一部分分别被覆盖。去除每个凹部中的未覆盖的金属层。牺牲的材料被去除。执行蚀刻处理以去除第一凹部中的剩余金属层并且将剩余的金属层保留在第二凹部中。

3. 发明申请

US20130122684A1 SEMICONDUCTOR PROCESS FOR REMOVING OXIDE LAYER 审中-公开
标题翻译：用于去除氧化层的半导体工艺
公开(公告)号：US20130122684A1
公开(公告)日：2013-05-16
申请号：US13293144
申请日：2011-11-10
申请人： Teng-Chun Hsuan , Ted Ming-Lang Guo , Chin-Cheng Chien
发明人： Teng-Chun Hsuan , Ted Ming-Lang Guo , Chin-Cheng Chien
IPC分类号： H01L21/265 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/02057 , H01L21/2652 , H01L21/28238 , H01L21/31116 , H01L21/823462 , H01L21/823481 , H01L21/823857 , H01L21/823878
摘要： A semiconductor process for removing oxide layers comprises the steps of providing a substrate having an isolation structure and a pad oxide layer, performing a dry cleaning process and a wet cleaning process to remove said pad oxide layer, forming a sacrificial oxide layer on said substrate, and performing an ion implantation process to form doped well regions on both sides of the isolation structure.
摘要翻译：用于去除氧化物层的半导体工艺包括以下步骤：提供具有隔离结构和衬垫氧化物层的衬底，执行干法处理和湿法清洁处理以去除所述焊盘氧化物层，在所述衬底上形成牺牲氧化物层，以及执行离子注入工艺以在隔离结构的两侧上形成掺杂阱区。

4. 发明申请

US20130026464A1 TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION 有权
标题翻译：使用X射线衍射测量半导体合金的测试图案
公开(公告)号：US20130026464A1
公开(公告)日：2013-01-31
申请号：US13189565
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L23/544
CPC分类号： H01L22/12 , H01L22/30
摘要： A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.
摘要翻译：使用X射线衍射（XRD）测量半导体合金的测试图案包括限定在晶片上的第N个区域和第N个区域，以及位于第一区域等等至第N区域的多个测试结构。相同区域中的测试结构具有彼此相同的尺寸，并且不同区域中的测试结构具有彼此不同的尺寸。

5. 发明申请

US20130026538A1 SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES 有权
标题翻译：具有外延结构的半导体器件
公开(公告)号：US20130026538A1
公开(公告)日：2013-01-31
申请号：US13189570
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/165 , H01L29/78
CPC分类号： H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
摘要翻译：具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。未掺杂的帽层还包括第一半导体材料和第二半导体材料。外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

6. 发明授权

US08716750B2 Semiconductor device having epitaxial structures 有权
标题翻译：具有外延结构的半导体器件
公开(公告)号：US08716750B2
公开(公告)日：2014-05-06
申请号：US13189570
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L29/66 , H01L29/165 , H01L29/78
CPC分类号： H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
摘要翻译：具有外延结构的半导体器件包括位于衬底上的栅极结构，在栅极结构的两侧形成在衬底中的外延结构，以及形成在外延结构上的未掺杂的帽层。外延结构包括掺杂剂，具有第一晶格常数的第一半导体材料和具有第二晶格常数的第二半导体材料，并且第二晶格常数大于第一晶格常数。未掺杂的帽层还包括第一半导体材料和第二半导体材料。外延结构中的第二半导体材料包括第一浓度，未掺杂帽层中的第二半导体材料至少包含第一浓度，第二浓度低于第一浓度。

7. 发明授权

US08519390B2 Test pattern for measuring semiconductor alloys using X-ray Diffraction 有权
$Test pattern for measuring semiconductor alloys using X-ray Diffraction$
标题翻译：使用X射线衍射测量半导体合金的测试图案
公开(公告)号：US08519390B2
公开(公告)日：2013-08-27
申请号：US13189565
申请日：2011-07-25
申请人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , I-Ming Lai , Chin-Cheng Chien
IPC分类号： H01L23/58
CPC分类号： H01L22/12 , H01L22/30
摘要： A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.
摘要翻译：使用X射线衍射（XRD）测量半导体合金的测试图案包括限定在晶片上的第N个区域和第N个区域，以及位于第一区域等等至第N区域的多个测试结构。相同区域中的测试结构具有彼此相同的尺寸，并且不同区域中的测试结构具有彼此不同的尺寸。

8. 发明授权

US08754448B2 Semiconductor device having epitaxial layer 有权
标题翻译：具有外延层的半导体器件
公开(公告)号：US08754448B2
公开(公告)日：2014-06-17
申请号：US13286222
申请日：2011-11-01
申请人： Chin-I Liao , Teng-Chun Hsuan , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , Chin-Cheng Chien
IPC分类号： H01L21/336 , H01L29/66 , H01L21/02 , H01L29/165 , H01L29/78
CPC分类号： H01L29/165 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
摘要翻译：半导体器件包括半导体衬底和多个晶体管。半导体衬底至少包括一个iso区域（即开放区域）和至少一个致密区域。晶体管分别设置在iso区域和致密区域中。每个晶体管至少包括一个源极/漏极区域。源极/漏极区域包括具有底部厚度和侧部厚度的第一外延层，并且底部厚度基本上大于或等于侧部厚度。

9. 发明申请

US20130105861A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER 有权
标题翻译：半导体器件及形成外延层的方法
公开(公告)号：US20130105861A1
公开(公告)日：2013-05-02
申请号：US13286222
申请日：2011-11-01
申请人： Chin-I Liao , Teng-Chun Hsuan , Chin-Cheng Chien
发明人： Chin-I Liao , Teng-Chun Hsuan , Chin-Cheng Chien
IPC分类号： H01L21/205 , H01L27/088
CPC分类号： H01L29/165 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823412 , H01L21/823418 , H01L27/088 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
摘要翻译：半导体器件包括半导体衬底和多个晶体管。半导体衬底至少包括一个iso区域（即开放区域）和至少一个致密区域。晶体管分别设置在iso区域和致密区域中。每个晶体管至少包括一个源极/漏极区域。源极/漏极区域包括具有底部厚度和侧部厚度的第一外延层，并且底部厚度基本上大于或等于侧部厚度。

10. 发明申请

US20120299157A1 SEMICONDUCTOR PROCESS AND FABRICATED STRUCTURE THEREOF 审中-公开
标题翻译：半导体工艺及其制造结构
公开(公告)号：US20120299157A1
公开(公告)日：2012-11-29
申请号：US13115125
申请日：2011-05-25
申请人： Teng-Chun Hsuan , Ted Ming-Lang Guo , Chin-Cheng Chien , Shu-Yen Chan
发明人： Teng-Chun Hsuan , Ted Ming-Lang Guo , Chin-Cheng Chien , Shu-Yen Chan
IPC分类号： H01L29/02 , H01L21/28
CPC分类号： H01L21/31116 , H01L21/0206 , H01L21/28123 , H01L21/76232
摘要： A semiconductor process includes the following steps. A substrate is provided, which includes an isolation structure and an oxide layer. The isolation structure divides the substrate into a first region and a second region. The oxide layer is located on the surface of the first region and the second region. A dry cleaning process is performed to remove the oxide layer. A dielectric layer is formed on the first region and the second region. A wet etching process is performed to remove at least one of the dielectric layers located on the first region and the second region. A semiconductor structure is fabricated by the above semiconductor process.
摘要翻译：半导体工艺包括以下步骤。提供了一种衬底，其包括隔离结构和氧化物层。隔离结构将衬底划分成第一区域和第二区域。氧化物层位于第一区域和第二区域的表面上。进行干洗处理以除去氧化物层。在第一区域和第二区域上形成介电层。执行湿蚀刻处理以去除位于第一区域和第二区域上的介电层中的至少一个。通过上述半导体工艺制造半导体结构。

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