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1. 发明授权

US07496817B2 Method for determining integrity of memory 有权
标题翻译：确定内存完整性的方法
公开(公告)号：US07496817B2
公开(公告)日：2009-02-24
申请号：US10708276
申请日：2004-02-20
申请人： Po-Wei Liu , Chang-Lien Wu
发明人： Po-Wei Liu , Chang-Lien Wu
IPC分类号： G01R31/30
CPC分类号： G11C29/28
摘要： A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.
摘要翻译：一种用于在多个操作环境下测试具有缺陷部分的存储器的完整性的方法包括在多个操作环境下测试具有缺陷部分的存储器，记录每个操作环境测试的结果，以及比较测试结果。如果结果相同，则声明具有缺陷部分的内存具有完整性。如果没有，具有缺陷部分的内存被声明为不完整。

2. 发明申请

US20050188286A1 METHOD FOR DETERMINING INTEGRITY OF MEMORY 有权
标题翻译：用于确定存储器的完整性的方法
公开(公告)号：US20050188286A1
公开(公告)日：2005-08-25
申请号：US10708276
申请日：2004-02-20
申请人： Po-Wei Liu , Chang-Lien Wu
发明人： Po-Wei Liu , Chang-Lien Wu
IPC分类号： G11C29/00 , G11C29/28
CPC分类号： G11C29/28
摘要： A method for testing the integrity of a memory with defective sections under a plurality of operating environments includes testing the memory with defective sections under a plurality of operating environments, recording results of each operating environment test, and comparing the results of the tests. If the results of are the same, the memory with defective sections is declared to have integrity. If not, the memory with defective sections is declared to not have integrity.
摘要翻译：一种用于在多个操作环境下测试具有缺陷部分的存储器的完整性的方法包括在多个操作环境下测试具有缺陷部分的存储器，记录每个操作环境测试的结果，以及比较测试结果。如果结果相同，则声明具有缺陷部分的内存具有完整性。如果没有，具有缺陷部分的内存被声明为不完整。

3. 发明申请

US20120257889A1 COMMUNICATION APPARATUS WITH TRANSMITTED RATE DETECTING FUNCTION AND METHOD THEREOF 有权
标题翻译：具有传输速率检测功能的通信装置及其方法
公开(公告)号：US20120257889A1
公开(公告)日：2012-10-11
申请号：US13441003
申请日：2012-04-06
申请人： Ting-Kang Chang , Po-Wei Liu , Jui-Chiang Wang , Jen-Hao Yeh
发明人： Ting-Kang Chang , Po-Wei Liu , Jui-Chiang Wang , Jen-Hao Yeh
IPC分类号： H04B10/08
CPC分类号： H04B10/0795 , H04L25/0262
摘要： A communication apparatus with transmitted rate detecting function and the method therefore is provided. The communication apparatus receives an input signal transmitted at a first rate or a second rate from a remote apparatus. The method includes setting the communication apparatus to operate at an initial receiving rate; sampling the input signal by a specific sampling frequency to generate a sample result; estimating the input transmitted rate of the input signal according to the sample result so as to set the receiving rate of the communication apparatus at a working rate; and communicating with the remote apparatus at the working rate. The second rate is higher than the first rate, and the specific sampling frequency is associated with the initial receiving rate.
摘要翻译：提供了一种具有传输速率检测功能的通信设备及其方法。通信装置从远程装置接收以第一速率或第二速率发送的输入信号。该方法包括将通信设备设置为以初始接收速率操作; 以特定采样频率对输入信号进行采样以产生采样结果; 根据采样结果估计输入信号的输入传输速率，以将通信设备的接收速率设定为工作速率; 并以工作速率与远程设备通信。第二速率高于第一速率，具体采样频率与初始接收速率相关。

4. 发明申请

US20110097859A1 METHOD OF FABRICATING CMOS TRANSISTOR 有权
标题翻译：制造CMOS晶体管的方法
公开(公告)号：US20110097859A1
公开(公告)日：2011-04-28
申请号：US12605377
申请日：2009-10-26
申请人： Wen-Tai Chiang , Chen-Hua Tsai , Cheng-Tzung Tsai , Po-Wei Liu
发明人： Wen-Tai Chiang , Chen-Hua Tsai , Cheng-Tzung Tsai , Po-Wei Liu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress in the strained channel. Therefore, the charge carrier mobility in a CMOS transistor is improved.
摘要翻译：制造CMOS晶体管的方法包括通过在退火期间用拉伸膜或压缩膜再结晶的非晶多晶硅形成应变通道。 C或Ge离子任选用于形成固相外延，以扩大应变通道中的应力。因此，提高了CMOS晶体管中的载流子迁移率。

5. 发明申请

US20090068824A1 FABRICATING METHOD OF SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件制造方法
公开(公告)号：US20090068824A1
公开(公告)日：2009-03-12
申请号：US11853539
申请日：2007-09-11
申请人： Po-Wei Liu , Cheng-Tzung Tsai
发明人： Po-Wei Liu , Cheng-Tzung Tsai
IPC分类号： H01L21/425
CPC分类号： H01L21/26506 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： A method for fabricating a semiconductor substrate is provided. A substrate having a region adjacent to a surface of the substrate as a channel region is provided. An ion implantation process is performed to form an amorphized silicon layer in the substrate below the channel region. A thermal treatment process is performed to re-crystallize the amorphized silicon layer so as to form an epitaxial material layer. The epitaxial material layer may enhance the stress on the channel region in the substrate.
摘要翻译：提供一种制造半导体衬底的方法。提供了具有与基板的表面相邻的区域作为沟道区域的基板。执行离子注入工艺以在通道区域下方的衬底中形成非晶化硅层。进行热处理工艺以使非晶化硅层再结晶以形成外延材料层。外延材料层可以增强衬底中的沟道区域上的应力。

6. 发明申请

US20050169300A1 APPARATUS AND RELATED METHOD FOR SERIALLY IMPLEMENTING DATA TRANSMISSION 审中-公开
标题翻译：用于串行实现数据传输的装置和相关方法
公开(公告)号：US20050169300A1
公开(公告)日：2005-08-04
申请号：US10906089
申请日：2005-02-02
申请人： Po-Wei Liu , Jung-You Feng , Chen-Chih Huang
发明人： Po-Wei Liu , Jung-You Feng , Chen-Chih Huang
IPC分类号： H03M9/00 , H04L12/66
CPC分类号： H03M9/00
摘要： A network interface includes a first network layer and a second network layer. The apparatus includes a first serial interface coupled to the first network layer and a second serial interface coupled to the second network layer. The first serial interface is for converting the first parallel data received from the first network layer into a first serial signal, and outputting the first serial signal serially. The second serial interface is for receiving and converting the first serial signal into the first parallel data, and sending the first parallel data to the second network layer.
摘要翻译：网络接口包括第一网络层和第二网络层。该装置包括耦合到第一网络层的第一串行接口和耦合到第二网络层的第二串行接口。第一串行接口用于将从第一网络层接收的第一并行数据转换为第一串行信号，并且串行地输出第一串行信号。第二串行接口用于将第一串行信号接收并转换成第一并行数据，并将第一并行数据发送到第二网络层。

7. 发明授权

US08774042B2 Communication apparatus with transmitted rate detecting function and method thereof 有权
标题翻译：具有传输速率检测功能的通信设备及其方法
公开(公告)号：US08774042B2
公开(公告)日：2014-07-08
申请号：US13441003
申请日：2012-04-06
申请人： Ting-Kang Chang , Po-Wei Liu , Jui-Chiang Wang , Jen-Hao Yeh
发明人： Ting-Kang Chang , Po-Wei Liu , Jui-Chiang Wang , Jen-Hao Yeh
IPC分类号： H04L12/26
CPC分类号： H04B10/0795 , H04L25/0262
摘要： A communication apparatus with transmitted rate detecting function and the method therefore is provided. The communication apparatus receives an input signal transmitted at a first rate or a second rate from a remote apparatus. The method includes setting the communication apparatus to operate at an initial receiving rate; sampling the input signal by a specific sampling frequency to generate a sample result; estimating the input transmitted rate of the input signal according to the sample result so as to set the receiving rate of the communication apparatus at a working rate; and communicating with the remote apparatus at the working rate. The second rate is higher than the first rate, and the specific sampling frequency is associated with the initial receiving rate.
摘要翻译：提供了一种具有传输速率检测功能的通信设备及其方法。通信装置从远程装置接收以第一速率或第二速率发送的输入信号。该方法包括将通信设备设置为以初始接收速率操作; 以特定采样频率对输入信号进行采样以产生采样结果; 根据采样结果估计输入信号的输入传输速率，以将通信设备的接收速率设定为工作速率; 并以工作速率与远程设备通信。第二速率高于第一速率，具体采样频率与初始接收速率相关。

8. 发明授权

US07714396B2 Metal-oxide semiconductor field effect transistor 有权
标题翻译：金属氧化物半导体场效应晶体管
公开(公告)号：US07714396B2
公开(公告)日：2010-05-11
申请号：US11309167
申请日：2006-07-05
申请人： Tzu-Yun Chang , Chen-Hua Tsai , Po-Wei Liu , Cheng-Tzung Tsai
发明人： Tzu-Yun Chang , Chen-Hua Tsai , Po-Wei Liu , Cheng-Tzung Tsai
IPC分类号： H01L27/088
CPC分类号： H01L21/823878 , H01L21/28061 , H01L21/28114 , H01L21/823418 , H01L21/823443 , H01L21/823468 , H01L21/823481 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/42376 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： The invention is directed to a method for forming a metal-oxide semiconductor field effect transistor. The method comprises steps of providing a substrate having a gate structure formed thereon, wherein a plurality of isolation structures are located in the substrate adjacent to both sides of the gate structure and then forming a first spacer on the sidewall of the gate structure. A portion of the substrate between the first spacer and the isolation structures is removed to form a recession and a source/drain layer is deposited in the recession, wherein the top surface of the source/drain layer is higher than the top surfaces of the isolation structures. A second spacer is formed on the isolation structures and at the sidewall of the source/drain layer and a metal silicide layer is formed on the source/drain layer.
摘要翻译：本发明涉及一种用于形成金属氧化物半导体场效应晶体管的方法。该方法包括提供其上形成有栅极结构的衬底的步骤，其中多个隔离结构位于与栅极结构的两侧相邻的衬底中，然后在栅极结构的侧壁上形成第一间隔物。在第一间隔物和隔离结构之间的衬底的一部分被去除以形成凹陷，并且在凹陷中沉积源极/漏极层，其中源/漏层的顶表面高于隔离层的顶表面结构。在隔离结构和源/漏层的侧壁处形成第二间隔物，并且在源极/漏极层上形成金属硅化物层。

9. 发明授权

US08507974B2 Fin-like field effect transistor (FinFET) non-volatile random access memory (NVRAM) device with bottom erase gate 有权
标题翻译：鳍状场效应晶体管（FinFET）具有底部擦除栅极的非易失性随机存取存储器（NVRAM）器件
公开(公告)号：US08507974B2
公开(公告)日：2013-08-13
申请号：US13115402
申请日：2011-05-25
申请人： Po-Wei Liu
发明人： Po-Wei Liu
IPC分类号： H01L29/792
CPC分类号： H01L29/42328 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7887 , H01L29/7923
摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; an insulator layer disposed over the semiconductor substrate; a fin structure disposed over the insulator layer, the fin structure having a source region, a drain region, and a channel region disposed between the source region and the drain region; a gate structure disposed adjacent to the channel region of the fin structure; and a doped region disposed in the semiconductor substrate below the channel region of the fin structure. The gate structure includes a first gate dielectric layer disposed adjacent to the fin structure, a second gate dielectric layer, a charge storing layer disposed between the first gate dielectric layer and the second gate dielectric layer, and a gate electrode layer disposed adjacent to the second gate dielectric layer.
摘要翻译：公开了一种用于制造FinFET器件的FinFET器件和方法。示例性的FinFET器件包括半导体衬底; 设置在半导体衬底上的绝缘体层; 翅片结构，其设置在所述绝缘体层上，所述鳍结构具有源区域，漏极区域和设置在所述源极区域和所述漏极区域之间的沟道区域; 邻近鳍片结构的沟道区域设置的栅极结构; 以及掺杂区域，其布置在所述鳍结构的沟道区域下方的所述半导体衬底中。栅极结构包括邻近翅片结构设置的第一栅极电介质层，第二栅极介电层，设置在第一栅极介电层和第二栅极电介质层之间的电荷存储层，以及邻近第二栅极电介质层设置的栅极电极层栅介质层。

10. 发明授权

US08440514B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08440514B2
公开(公告)日：2013-05-14
申请号：US12101725
申请日：2008-04-11
申请人： Po-Wei Liu , Cheng-Tzung Tsai , Wen-Tai Chiang
发明人： Po-Wei Liu , Cheng-Tzung Tsai , Wen-Tai Chiang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/6656 , H01L29/6659 , H01L29/7848
摘要： A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.
摘要翻译：提供一种制造半导体器件的方法。在基板上形成栅极结构。执行第一掺杂剂注入和第一应变原子注入。此后，在栅极结构的侧壁上形成间隔物。进行第二掺杂剂注入和第二应变原子注入。进行固相外延退火处理以形成由栅极结构旁边的由半导体化合物固相外延层制成的源区和漏区。

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