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1. 发明授权

US06369730B1 Sigma-delta analog-to-digital converter 有权
标题翻译： Sigma-delta模数转换器
公开(公告)号：US06369730B1
公开(公告)日：2002-04-09
申请号：US09553602
申请日：2000-04-20
申请人： Pieter G. Blanken , Eric J. Van der Zwan , Eise C. Dijkmans
发明人： Pieter G. Blanken , Eric J. Van der Zwan , Eise C. Dijkmans
IPC分类号： H03M300
CPC分类号： H03M3/348 , H03M3/43
摘要： Sigma-delta analog-to-digital converter topology with an error signal branch including a subtractor (10), a loop filter (4), and a quantizer (6), and a feedback branch including a digital-to-analog converter (8). The gain error caused by a return-to-zero switch in the feedback branch is cancelled by moving the return-to-zero switch (20) to the signal error branch.
摘要翻译：具有包括减法器（10），环路滤波器（4）和量化器（6）的误差信号分支的Σ-Δ模数转换器拓扑，以及包括数模转换器（8）的反馈分支）。通过将返回到零开关（20）移动到信号错误分支来消除由反馈分支中的归零开关引起的增益误差。

2. 发明授权

US06584157B1 Receiver having integrated mixer and Sigma-Delta analog-to digital conversion 有权
标题翻译：接收机具有集成混频器和Sigma-Delta模数转换
公开(公告)号：US06584157B1
公开(公告)日：2003-06-24
申请号：US09342827
申请日：1999-06-29
申请人： Eric J. Van Der Zwan , Eise C. Dijkmans , William Donaldson , Anthony D. Sayers
发明人： Eric J. Van Der Zwan , Eise C. Dijkmans , William Donaldson , Anthony D. Sayers
IPC分类号： H04B1406
CPC分类号： H03M3/41 , H03M3/43
摘要： A receiver with an integrated mixer/Sigma-Delta Modulator configuration for digitizing a relatively low-bandwidth signal modulated on a high-frequency carrier, for example in a radio receiver. The Sigma-Delta Modulator has an continuous-time loop filter (F1, F2) with anti-aliasing characteristics which eliminate the need for a separate lowpass filter between the mixer (MX) and the Sigma-Delta Modulator.
摘要翻译：具有集成混频器/Σ-Δ调制器配置的接收机，用于数字化在高频载波上调制的相对低带宽的信号，例如在无线电接收机中。 Sigma-Delta调制器具有具有抗混叠特性的连续时间环路滤波器（F1，F2），无需混频器（MX）和Σ-Δ调制器之间的单独低通滤波器。

3. 发明授权

US06404367B1 Sigma-delta modulator with improved gain accuracy 有权
标题翻译：增益精度提高的Σ-Δ调制器
公开(公告)号：US06404367B1
公开(公告)日：2002-06-11
申请号：US09139242
申请日：1998-08-25
申请人： Eric J. Van der Zwan , Eise C. Dijkmans
发明人： Eric J. Van der Zwan , Eise C. Dijkmans
IPC分类号： H03M300
CPC分类号： H03M3/34 , H03M3/424
摘要： Sigma-delta modulator in which the gain stage (20) of the input network and the gain stage (22) of the feedback network are regularly interchanged (“chopped”). This averages out the difference between the two gain stages, thus defining the gain of the system accurately. The difference in gain between the two gain stages is modulated on the chopping frequency, which may be outside the frequency band of interest. Furthermore, by using fully differential circuitry the chopping can be effected in such a manner that the offset and flicker noise of the two gain stages are modulated to the chopping frequency.
摘要翻译：其中输入网络的增益级（20）和反馈网络的增益级（22）经常互换（“切碎”）的Σ-Δ调制器。这平均了两个增益级之间的差异，从而准确地定义了系统的增益。两个增益级之间的增益差被调制在斩波频率上，斩波频率可能在感兴趣的频带之外。此外，通过使用全差分电路，可以以两个增益级的偏移和闪烁噪声调制到斩波频率的方式实现斩波。

4. 发明授权

US4706039A Amplifier arrangement 失效
标题翻译：放大器布置
公开(公告)号：US4706039A
公开(公告)日：1987-11-10
申请号：US838729
申请日：1986-03-11
申请人： Eise C. Dijkmans , Joseph G. G. Raets , Norbert J. L. Philips
发明人： Eise C. Dijkmans , Joseph G. G. Raets , Norbert J. L. Philips
IPC分类号： H03F3/30 , H03F1/02 , H03F3/20 , H03F3/213 , H03G3/30
CPC分类号： H03F1/0244
摘要： A class-G amplifier comprises first, second and third terminals connected to a load, first supply voltage (V.sub.1) and second supply voltage (V.sub.2), respectively, where V.sub.2 >V.sub.1. First (T.sub.1) and second (T.sub.2) transistors are series-connected between the first and third terminals with the collector of T.sub.1 coupled via first diode (D.sub.1) to the second terminal. A third emitter follower transistor (T.sub.3) has a B/E junction coupled between a signal input terminal and base of T.sub.1. A first current source (5) couples the third terminal and third transistor. A driver circuit includes a first current path between the third terminal and emitter of T.sub.3 comprising, in series, a second current source (7), a fourth transistor (T.sub.5) and second diode (D.sub.4). A second current path between a junction point (3) and common point (11) comprises, in series, third (D.sub.2) and fourth (D.sub.3) diodes and a third current source (8). Base of fourth transistor is connected to junction (9) and its collector is connected to third current source via fifth diode (D.sub.5). A low input voltage cuts off second transistior so first transistor connected to second terminal. Above a given voltage, driver circuit turns second transistor on so first transistor connected to third terminal. The output (2) thereby attains a voltage equal to second supply voltage (V.sub.2) minus one B/E voltage.
摘要翻译： G类放大器包括分别连接到负载的第一，第二和第三端子，其中V2> V1分别是第一电源电压（V1）和第二电源电压（V2）。第一（T1）和第二（T2）晶体管串联在第一和第三端子之间，T1的集电极经由第一二极管（D1）耦合到第二端子。第三射极跟随器晶体管（T3）具有耦合在信号输入端和T1基极之间的B / E结。第一电流源（5）耦合第三端子和第三晶体管。驱动器电路包括在T3的第三端子和发射极之间的第一电流路径，其包括串联的第二电流源（7），第四晶体管（T5）和第二二极管（D4）。连接点（3）和公共点（11）之间的第二电流路径包括串联的第三（D2）和第四（D3）二极管和第三电流源（8）。第四晶体管的基极连接到结（9），其集电极通过第五二极管（D5）连接到第三电流源。低输入电压切断第二转换器，因此第一晶体管连接到第二端子。在给定电压以上，驱动电路使第二晶体管导通，因此第一晶体管连接到第三端。输出（2）由此获得等于第二电源电压（V2）减去一个B / E电压的电压。

5. 发明授权

US4706035A High efficiency amplifier having a bootstrap capacitor 失效
标题翻译：具有自举电容器的高效放大器
公开(公告)号：US4706035A
公开(公告)日：1987-11-10
申请号：US838728
申请日：1986-03-11
申请人： Eise C. Dijkmans , Joseph G. G. Raets , Norbert J. L. Philips
发明人： Eise C. Dijkmans , Joseph G. G. Raets , Norbert J. L. Philips
IPC分类号： H03F3/30 , H03F1/02 , H03F3/20 , H03G3/30 , H03F1/38
CPC分类号： H03F1/0244 , H03F1/0233
摘要： A high-efficiency class-G type amplifier comprises a first transistor (T.sub.1), having its collector connected to a first supply voltage (V.sub.1) via a first diode (D.sub.1) and a second transistor (T.sub.2), connected in series with the first transistor and which has its collector connected to a second supply voltage (V.sub.2). The series arrangement of a second (D.sub.2), a third (D.sub.3) and a fourth diode (D.sub.4) is connected between the bases of the first and the second transistor (T.sub.1, T.sub.2) the fourth diode (D.sub.4) is poled in a direction opposite to that of the second (D.sub.2) and the third diode (D.sub.3). The series arrangement of a first resistor (R.sub.1) and the emitter-collector path of a first current-source transistor (T.sub.4) connects the second supply voltage to the anode of the fourth diode (D.sub.4). The junction point (5) between the first resistor (R.sub.1) and the current-source transistor (T.sub.4) is connected to the output (2) by means of a capacitor (C.sub.1). This arrangment drives the output to a voltage substantially equal to the second supply voltage (V.sub.2).
摘要翻译：高效率的G类放大器包括第一晶体管（T1），其第一晶体管（T1）经由第一二极管（D1）和第二晶体管（T2）与第一电源电压（V1）连接，与第一晶体管晶体管，其集电极连接到第二电源电压（V2）。第二（D2），第三（D3）和第四二极管（D4）的串联布置连接在第一和第二晶体管（T1，T2）的基极之间，第四二极管（D4）在方向与第二（D2）和第三二极管（D3）的相反。第一电阻（R1）和第一电流源晶体管（T4）的发射极 - 集电极路径的串联布置将第二电源电压连接到第四二极管（D4）的阳极。第一电阻器（R1）和电流源晶体管（T4）之间的连接点（5）通过电容器（C1）连接到输出端（2）。该布置将输出驱动到基本上等于第二电源电压（V2）的电压。

6. 发明授权

US4466013A Tapped integrated resistor 失效
标题翻译：开关集成电阻
公开(公告)号：US4466013A
公开(公告)日：1984-08-14
申请号：US525350
申请日：1983-08-22
申请人： Rudy J. van de Plassche , Eise C. Dijkmans
发明人： Rudy J. van de Plassche , Eise C. Dijkmans
IPC分类号： H01L27/04 , H01L21/822 , H01L27/08 , H01L29/8605 , H01L27/02
CPC分类号： H01L27/0802 , H01L29/8605
摘要： The invention relates to an integrated resistor formed in an epitaxial layer and provided with at least one tap. In order to reduce field effect action between the resistor and the epitaxial layer, the voltage on the two ends of the epitaxial layer underneath the resistor tracks the voltage on the two ends of the resistor. Moreover, the epitaxial layer is short-circuited by means of buried layers at the locations where the resistance layer also exhibits a short-circuit, such as underneath the contact area of the tap.
摘要翻译：本发明涉及一种形成在外延层中并具有至少一个分接头的集成电阻器。为了减小电阻和外延层之间的场效应，电阻下方的外延层两端的电压跟踪电阻两端的电压。此外，外延层通过掩埋层在电阻层也表现出短路的位置（例如在接头的接触区域下方）短路。

7. 发明授权

US4366346A Artificial reverberation apparatus 失效
标题翻译：人造混响装置
公开(公告)号：US4366346A
公开(公告)日：1982-12-28
申请号：US140288
申请日：1980-04-14
申请人： Eise C. Dijkmans , Nico V. Franssen, deceased , by Friedrich J. De Haan, administrator
发明人： Eise C. Dijkmans , Nico V. Franssen, deceased , by Friedrich J. De Haan, administrator
IPC分类号： H03H7/30 , G10K15/12 , H03H11/26 , G01K11/00
CPC分类号： G10K15/12
摘要： Artificial reverberation apparatus comprising a delay device (1) provided with a feedback circuit (5) and a feed-forward circuit (6) having a gain equal and opposite to that of the feedback circuit if the gain in the delay device is unity. In order to simulate a second echo having a different delay time using a minimum number of circuit components, the foregoing reverberation circuit is included in cascade with a second delay device (11) and the resulting combination is provided with its own feedback circuit (15) and feed-forward circuit (16). In order to simulate a third echo having yet another delay time, the resulting circuit may be included in cascade with a third delay device (21) with the resulting combination having its own feedback circuit (25 ) and feed forward circuit (26).
摘要翻译：如果延迟装置中的增益为1，则包括具有反馈电路（5）的延迟装置（1）和前馈电路（6）的人造混响装置，其具有与反馈电路的增益相等的增益。为了使用最小数量的电路组件来模拟具有不同延迟时间的第二回波，上述混响电路与第二延迟装置（11）级联并且所得到的组合被提供有其自己的反馈电路（15）和前馈电路（16）。为了模拟具有另一个延迟时间的第三回波，所得到的电路可以与第三延迟装置（21）级联包括，所得到的组合具有其自己的反馈电路（25）和前馈电路（26）。

8. 发明授权

US06636170B1 Signal converter with digital/analog conversion and noise-dependent variability of output signal bandwidth 失效
标题翻译：具有数字/模拟转换和输出信号带宽的噪声依赖变化的信号转换器
公开(公告)号：US06636170B1
公开(公告)日：2003-10-21
申请号：US09534213
申请日：2000-03-24
申请人： Eise C. Dijkmans
发明人： Eise C. Dijkmans
IPC分类号： H03M166
CPC分类号： H03H17/0657
摘要： A signal converter includes a digital/analog converter and a low pass filter. The converter includes control means for amending the ratio of sampling frequencies of the D/A input signal and the D/A output signal or of the low pass filter.
摘要翻译：信号转换器包括数/模转换器和低通滤波器。转换器包括用于修正D / A输入信号和D / A输出信号或低通滤波器的采样频率比的控制装置。

9. 发明授权

US5955923A Amplifier with reduced cross-over distortion 失效
标题翻译：具有减小的交叉失真的放大器
公开(公告)号：US5955923A
公开(公告)日：1999-09-21
申请号：US538510
申请日：1995-10-03
申请人： Eise C. Dijkmans , Anthonius F. Duisters
发明人： Eise C. Dijkmans , Anthonius F. Duisters
IPC分类号： H03F1/32 , H03F3/26
CPC分类号： H03F1/3217
摘要： An amplifier arrangement having a first and a second output transistor, which are drain-connected to the output terminal. A driver stage (100), prevents the output transistors from becoming non-conductive, thereby reducing cross-over distortion. This is achieved by applying an input signal via the sources of a source coupled transistor pair to the gates of the output transistors. Additional source followers are provided for defining gate-sources voltages which prevent the output transistors from becoming non-conductive.
摘要翻译：一种具有第一和第二输出晶体管的放大器装置，其漏极连接到输出端子。驱动器级（100）防止输出晶体管变得不导通，从而减少交叉失真。这通过将源极耦合晶体管对的源极输入到输出晶体管的栅极来实现。提供附加的源极跟随器来定义栅极 - 源极电压，从而防止输出晶体管变得不导通。

10. 发明授权

US5587678A Integrated circuit having an output stage with a Miller capacitor 失效
标题翻译：具有输出级的集成电路具有米勒电容器
公开(公告)号：US5587678A
公开(公告)日：1996-12-24
申请号：US437750
申请日：1995-05-09
申请人： Eise C. Dijkmans
发明人： Eise C. Dijkmans
IPC分类号： H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0948 , H03F3/26
CPC分类号： H03K19/00361
摘要： An integrated circuit, includes an output stage with an input which is coupled to a first and a second gate of an NMOS transistor and a PMOS transistor, respectively, and an output which is connected to a first and a second supply terminal via the PMOS transistor and the NMOS transistor, respectively. The output is coupled to the first gate via a series connection of a Miller capacitor and a switching circuit. The Miller capacitor limits the rate of increase of the voltage on the output, thus preventing interference. The switching circuit is rendered non-conductive ahead of the switching over from logic low to logic high. This prevents sudden discharging of the Miller capacitor which would otherwise cause interference itself.
摘要翻译：一种集成电路，包括输出级，输出端分别耦合到NMOS晶体管和PMOS晶体管的第一和第二栅极，以及经由PMOS晶体管连接到第一和第二电源端的输出端和NMOS晶体管。输出通过米勒电容器和开关电路的串联连接耦合到第一门极。米勒电容器限制输出电压的增加速率，从而防止干扰。切换电路在从逻辑低电平切换到逻辑高电平之前变为不导通。这样可以防止米勒电容的突然放电，否则会造成本身的干扰。

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