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1. 发明授权

US4473900A Modular structure for multistage PCM switching network 失效
标题翻译：多级PCM交换网络的模块化结构
公开(公告)号：US4473900A
公开(公告)日：1984-09-25
申请号：US339101
申请日：1982-01-13
申请人： Piero Belforte , Mario Bondonno , Enzo Garetti , Giancarlo Guaschino , Luciano Pilati
发明人： Piero Belforte , Mario Bondonno , Enzo Garetti , Giancarlo Guaschino , Luciano Pilati
IPC分类号： H04Q3/545 , H04Q11/04 , H04J3/00
CPC分类号： H04Q11/0407
摘要： A five-stage PCM switching network of an automatic telephone exchange is divided into a set of outer modular units each including a first-stage and a fifth-stage matrix, a set of inner modular units each including a second-stage and a fourth-stage matrix, and a set of central modular units each including a pair of third-stage matrices. Each modular unit is provided with an individual base-level microprocessor controlling the switching of its matrices and the checking of their performance with the aid of ancillary equipment including transceivers sending back outgoing signals and samplers delivering bytes from corresponding time slots at opposite ends of an established signal path to a comparator in the associated microprocessor. Each set is divided into several subsets provided with respective intermediate-level microprocessors which control their base-level microprocessors; a top-level microprocessor, responsive to commands from a central controller, dialogues with the intermediate-level microprocessors for setting up and discontinuing calling connections between incoming PCM lines joined to inputs of the first-stage matrices and outgoing PCM lines joined to outputs of the fifth-stage matrices.
摘要翻译：自动电话交换机的五级PCM交换网络被分为一组外部模块单元，每个外部模块单元包括第一级和第五级矩阵，一组内部模块单元，每组包括第二级和第四级，阶段矩阵，以及一组中央模块单元，每个中心模块单元包括一对第三级矩阵。每个模块单元都配备有一个单独的基本级微处理器，它们可以通过辅助设备的辅助设备来控制其矩阵的切换和检查其性能，包括收发器发回输出信号和采样器，从已建立的相对端的相应时隙到相关微处理器中比较器的信号通路。每个集合被分成几个子集，每个子集具有控制其基本级微处理器的各个中级微处理器; 响应于来自中央控制器的命令的顶级微处理器，与中级微处理器的对话，用于建立和中断连接到第一级矩阵的输入的输入PCM线和连接到第一级矩阵的输出的输出PCM线之间的呼叫连接第五阶段矩阵。

2. 发明授权

US4550398A Modular self-routing PCM switching network for distributed-control telephone exchange 失效
标题翻译：模块化自路由PCM交换网络用于分布式控制电话交换
公开(公告)号：US4550398A
公开(公告)日：1985-10-29
申请号：US506709
申请日：1983-06-22
申请人： Piero Belforte , Enzo Garetti , Luciano Pilati
发明人： Piero Belforte , Enzo Garetti , Luciano Pilati
IPC分类号： H04Q3/52 , H04Q11/04 , H04J3/12
CPC分类号： H04Q11/04
摘要： An automatic exchange of a telephone system comprises a PCM switching network with a plurality of cascaded stages for establishing temporal and spatial connections between incoming channels on input lines of the first stage and outgoing channels on output lines of the last stage in response to commands from external controllers dialoguing with internal controllers of the network. Pairs of switching matrices forming part of nonadjacent stages are combined into modular switching units each provided with its own internal controller. Routing instructions are transmitted from an external controller to a first internal controller which selects a signal path through the matrices of its own switching unit and informs a second internal controller of that selection whereupon the latter extends the path through an adjoining switching unit, and so on until the connection is completed. With digital message words such as speech bytes traveling in a forward direction from the input side to the output side of the network, the instruction words pertaining thereto move in the opposite direction over the same interstage links; the two paths are mutually conjugate within each switching unit, their matrices being bypassed by the routing instructions.
摘要翻译：电话系统的自动交换包括具有多个级联级的PCM交换网络，用于响应于来自外部的命令建立在第一级输入线路上的输入信道和最后级输出线路上的输出信道之间的时间和空间连接控制器与网络的内部控制器对话。构成不相邻级的一部分的开关矩阵的对组合成各自具有其自己的内部控制器的模块化开关单元。路由指令从外部控制器发送到第一内部控制器，该第一内部控制器通过其自己的切换单元的矩阵来选择信号路径，并且向第二内部控制器通知该选择，然后通过相邻的切换单元延伸路径，等等直到连接完成。利用从网络的输入侧到输出侧向前行进的语音字节等数字消息字，与其相关的指示字在相同的级间链路上相反移动; 两个路径在每个切换单元内相互共轭，它们的矩阵被路由指令旁路。

3. 发明授权

US3958086A Telephone-signal receiver for switching exchanges having centralized logic circuits 失效
标题翻译：具有集中逻辑电路的交换机的电话信号接收机
公开(公告)号：US3958086A
公开(公告)日：1976-05-18
申请号：US517017
申请日：1974-10-22
申请人： Piero Calcagno , Enzo Garetti
发明人： Piero Calcagno , Enzo Garetti
IPC分类号： H04Q3/54 , H04M3/22
CPC分类号： H04Q3/54
摘要： Switching criteria are transmitted over a plurality of trunk lines to a central office of a telecommunication system in the form of a set of binary signals modulated on three carriers for each trunk line, the triads of carriers being cyclically sampled and demodulated. During each sampling interval t.sub.i allocated to a particular trunk G.sub.i within a cycle, a locally generated identification code of that trunk is transmitted to each of three sections of a read-only memory MS, each memory section permanently storing four different threshold values for the length of "on" signals (1) and "off" signals (0). Integrators IN, rejecting spurious changeovers from one type of signal to the other, feed respective counters CT via respective coincidence circuits CFR which receive from a register MG the bits of the preceding cycle and reset arithmetic units .sigma. in these counters whenever there is a definite change in the type of signal received; each counter CT, emitting a count which increases by 1 in each new cycle, is maintained at its maximum count (unless previously reset) as long as no change occurs. The count of each counter is compared with the several threshold values, stored in the associated memory section, in a corresponding section of a comparator CMP whose output is delivered to a processor AC.
摘要翻译：将切换标准通过多条干线传送到电信系统的中心局，以对于每条中继线在三个载波上调制的一组二进制信号的形式，三比特载波被循环采样和解调。在一个周期内分配给特定干线Gi的每个采样间隔ti期间，将该干线的本地生成的识别码发送到只读存储器MS的三个部分中的每一个，每个存储部分永久地存储四个不同的阈值的“开”信号（1）和“关”信号（0）。积分器IN拒绝从一种类型的信号到另一种信号的虚假切换通过相应的重合电路CFR馈送相应的计数器CT，每当存在确定的变化时，它们从寄存器MG接收前一周期的比特和这些计数器中的复位算术单元sigma 在收到的信号类型中; 只要不发生变化，每个计数器CT发出每个新循环中增加1的计数，保持在其最大计数（除非事先复位）。将每个计数器的计数与存储在相关联的存储器部分中的几个阈值进行比较，其中比较器CMP的输出被递送到处理器AC的相应部分中。

4. 发明授权

US4345319A Self-correcting, solid-state-mass-memory organized by bits and with reconfiguration capability for a stored program control system 失效
标题翻译：自校正固态大容量存储器由位组成，并具有存储的程序控制系统的重新配置能力
公开(公告)号：US4345319A
公开(公告)日：1982-08-17
申请号：US051246
申请日：1979-06-22
申请人： Vincenzo Bernardini , Enzo Garetti , Renato Manfreddi
发明人： Vincenzo Bernardini , Enzo Garetti , Renato Manfreddi
IPC分类号： G06F12/16 , G06F3/00 , G06F11/10 , G11C19/28 , G11C29/00 , G11C11/40
CPC分类号： G11C29/80 , G06F11/1008 , G06F11/1076 , G06F3/007 , G11C19/287
摘要： A mass memory for use with telecommunication equipment comprises a plurality of memory units associated with respective controllers. Each memory unit includes a command module, dialoguing with the associated controller, and a multiplicity of memory modules for the storage of respective information and redundancy bits of a number of data words, one bit of each word being written in an integrated charge-transfer circuit individually assigned thereto and being continuously recirculated when the memory unit is idle. The command module contains a corrective logic which includes a generator of redundancy bits and intervenes during reading and writing phases. An input/output unit, also forming part of the command module, may comprise a switching circuit including a set of multiplexers which may be selectively operated by instructions from the controller to replace a defective memory module by a spare module whose bit-storing circuits already contain the data of the defective module or can receive them in a reinitialization operation. Instead of a single command module, three such modules synchronized with one another can be used to control the reading and writing through majority logic.
摘要翻译：与电信设备一起使用的大容量存储器包括与相应控制器相关联的多个存储器单元。每个存储器单元包括与相关联的控制器对话的命令模块和用于存储多个数据字的各个信息和冗余位的多个存储器模块，每个字的一位被写入集成电荷传输电路当存储器单元空闲时被单独地分配给它并且被连续再循环。命令模块包含一个校正逻辑，其中包括冗余位发生器，并在读写阶段进行干预。还构成命令模块的一部分的输入/输出单元可以包括切换电路，其包括一组多路复用器，其可以由来自控制器的指令选择性地操作，以通过其位存储电路已经存在的备用模块来替换有缺陷的存储器模块包含有缺陷模块的数据，或者可以在重新初始化操作中接收它们。代替单个命令模块，可以使用彼此同步的三个这样的模块来控制通过多数逻辑的读取和写入。

5. 发明授权

US4216532A Self-correcting solid-state mass memory organized by words for a stored-program control system 失效
标题翻译：通过存储程序控制系统的单词组织的自校正固态大容量存储器
公开(公告)号：US4216532A
公开(公告)日：1980-08-05
申请号：US17037
申请日：1979-03-02
申请人： Enzo Garetti , Renato Manfreddi
发明人： Enzo Garetti , Renato Manfreddi
IPC分类号： G06F12/16 , G06F3/00 , G06F11/10 , G11C19/28 , G11C27/04 , H04Q3/545 , G11C13/00
CPC分类号： G06F11/1008 , G06F11/1076 , G06F3/007 , G11C19/287 , H04Q3/54591 , H04Q2213/13168
摘要： A stored-program control system for a telephone exchange or the like comprises processing units coupled to several main memories and to several mass memories. Each mass memory includes one or more memory modules each with one or more rows of shift registers of the charge-coupled type, operating in a serial-parallel-serial mode, and a control module equipped with a self-correcting logic and a microprogrammed time base.
摘要翻译：用于电话交换机等的存储程序控制系统包括耦合到几个主存储器和几个质量存储器的处理单元。每个大容量存储器包括一个或多个存储器模块，每个存储器模块具有一个或多个电荷耦合类型的移位寄存器行，串行并行串行模式操作，以及配备有自校正逻辑和微程序时间的控制模块基础。

6. 发明授权

US4009468A Logic network for programmable data concentrator 失效
标题翻译：可编程数据集中器的逻辑网络
公开(公告)号：US4009468A
公开(公告)日：1977-02-22
申请号：US565114
申请日：1975-04-04
申请人： Piero Calcagno , Enzo Garetti , Gunter Lobisch
发明人： Piero Calcagno , Enzo Garetti , Gunter Lobisch
IPC分类号： G06F7/76 , H04Q3/00 , H04J3/00
CPC分类号： G06F7/762
摘要： For the selective energization of combinations of up to m data outputs of a data concentrator with n data inputs (n > m), the concentrator is provided with n control inputs energizable in various patterns. The concentrator comprises a logic network with an enabling section and a performing section, each in the form of a truncated orthogonal matrix with m rows and n columns of gating circuits. In each matrix the number of gating circuits decreases from n in the first row to (n-m+1) in the last row. The gating circuits of each column of the enabling matrix are connected in parallel to a respective control input whose energization gives rise to an internal activation signal in one of these circuits and simultaneously blocks the circuits of the same row while unblocking those on a diagonal for possible activation by the energization of one of the following control inputs; thus, only one activation signal can come from any row and the number of such activation signals -- up to m -- depends on the number of energized control inputs. The gating circuits of the performing section consist each of a coincidence (NAND or AND) gate connected on the one hand to an output terminal of the corresponding circuit of the enabling matrix and on the other hand to a data input, the gates of each column being connected to the same data input in parallel; the gates of each row work into a common summing circuit (NAND or OR gate) energizing a respective data output if an activation signal is applied to a gating circuit of that row connected to an energized data input.
摘要翻译：对于具有n个数据输入（n> m）的数据集中器的多达m个数据输出的组合的选择性激励，集中器被提供有以各种模式激励的n个控制输入。集线器包括具有使能部分和执行部分的逻辑网络，每个部分具有m行和n列门控电路的截断的正交矩阵的形式。在每个矩阵中，选通电路的数量从最后一行的第一行的n减少到（n-m + 1）。使能矩阵的每列的门控电路并联连接到相应的控制输入，其通电在这些电路中的一个中产生内部激活信号，并且同时阻塞同一行的电路，同时解除对角线上的那些电路可能通过以下控制输入之一的激励来激活; 因此，只有一个激活信号可以来自任何行，并且这种激活信号的数量（直到m）取决于激励的控制输入的数量。执行部分的门控电路包括一方面连接到使能矩阵的相应电路的输出端的一致（NAND或AND）门，另一方面连接到数据输入，每列的门并行连接到相同的数据输入; 如果激活信号被施加到连接到通电数据输入的该行的选通电路，则每行的栅极工作到公共求和电路（NAND或或门）中，激励相应的数据输出。

7. 发明授权

US3988543A Inter-office signaling system for telecommunication network 失效
标题翻译：电信网络的室内信令系统
公开(公告)号：US3988543A
公开(公告)日：1976-10-26
申请号：US564549
申请日：1975-04-02
申请人： Cristiano Dall'Olio , Enzo Garetti
发明人： Cristiano Dall'Olio , Enzo Garetti
IPC分类号： H04Q3/545 , H04J1/14
CPC分类号： H04Q3/545
摘要： Message transmission between subscriber stations served by different central offices takes place via frequency-division channels through the intermediary of couplers recognizing different line signals, specifically pulse sequences modulating the amplitude of a fixed-frequency oscillation on a test wire, to initiate certain switching operations. A processor, responding to these signals either upon initiation of a connection or in the course thereof, summons an available modem which is temporarily connected to the associated coupler and emits a characteristic a-c signal picked up by a remote coupler at another exchange which thereupon causes its processor to connect another modem to it, to the exclusion of any subscriber line to which that coupler may have been previously connected. The two modems then intercommunicate and work into respective logic networks which, under their control, carry out the requisite switching operations whereupon the modems are released upon establishment or re-establishment of the desired connection.
摘要翻译：由不同中心局服务的用户站之间的消息传输通过分频信道通过耦合器中间识别不同的线路信号，特别是调制测试线上的固定频率振荡的幅度的脉冲序列来发起特定的交换操作。处理器响应于这些信号或者在连接开始时或在其过程中，召唤一个可用的调制解调器，该调制解调器临时连接到相关联的耦合器，并且发射由另一个交换机上的远程耦合器拾取的特征交流信号，处理器连接另一个调制解调器，以排除该耦合器以前可能连接到的任何用户线路。然后，两个调制解调器相互通信并工作到各自的逻辑网络，在它们的控制下，执行必要的切换操作，由此在建立或重新建立期望的连接时释放调制解调器。

8. 发明授权

US3980833A Call monitor for telecommunication exchange 失效
标题翻译：呼叫监控器用于电信交换
公开(公告)号：US3980833A
公开(公告)日：1976-09-14
申请号：US572336
申请日：1975-04-28
申请人： Piero Calcagno , Enzo Garetti
发明人： Piero Calcagno , Enzo Garetti
IPC分类号： H04Q11/04 , H04J3/14
CPC分类号： H04Q11/0407
摘要： A call monitor for a telephone exchange, including a processor intervening in the establishment of a connection between associated line links with the aid of a switching network, comprises a first memory storing information about each line link and a second memory containing codes that identify all possible states of a connection of interest to the processor along with all intervening conditions termed evolutions. During a time slot allocated to a particular line link, a multibit comparator receives data from the first memory concerning a connection involving that line link, along with updating information from the line link itself, on one set of inputs and further receives, on another set of inputs, a succession of evolutionary codes read out from the second memory until a match is detected; the read-out is then terminated and an instruction, if required, is sent to the processor and/or to the switching network.
摘要翻译：用于电话交换机的呼叫监视器，包括借助于交换网络建立相关线路链路之间的连接的处理器，包括存储关于每条线路链路的信息的第一存储器和包含识别所有可能的代码的代码的第二存储器处理器感兴趣的连接状态以及称为演化的所有中间条件。在分配给特定线路链路的时隙期间，多比特比较器从一个第一存储器接收关于涉及该线路链路的连接的数据以及来自线路链路本身的信息，并在另一组上接收另一组的输入，从第二存储器读出的连续的进化代码，直到检测到匹配; 然后终止读出，并且如果需要，则将指令发送到处理器和/或交换网络。

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