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1. 发明授权

US06453443B1 Method for cell modeling and timing verification of chip designs with voltage drop 有权
标题翻译：具有电压降的芯片设计的电池建模和定时验证方法
公开(公告)号：US06453443B1
公开(公告)日：2002-09-17
申请号：US09835028
申请日：2001-04-16
申请人： Pi-Cheng Chen , Wen-Hao Chen , Ming-Chyuan Chen , Hsien-Te Chen
发明人： Pi-Cheng Chen , Wen-Hao Chen , Ming-Chyuan Chen , Hsien-Te Chen
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： In the present invention a method is described to produce a whole chip timing verification that includes the effects of voltage variation on delay. This is done by creating a netlist, defining cell input and output (I/O) delay paths, and calculating the difference timing caused by differences in power supply voltage. The incremental I/O path delay is calculated by adding delay changes caused by all power pins. Whole chip timings are generated without consideration to voltage drops and then modified using the incremental path delay. The modified whole chip timing data file is used with traditional timing verification tools to perform a whole chip cell level timing verification.
摘要翻译：在本发明中，描述了一种方法来产生包括电压变化对延迟的影响的整个芯片定时验证。这通过创建网表，定义单元输入和输出（I / O）延迟路径以及计算由电源电压差异引起的差异定时来完成。通过增加由所有电源引脚引起的延迟更改来计算增量I / O路径延迟。在不考虑电压降的情况下生成整个芯片定时，然后使用增量路径延迟进行修改。经修改的全芯片定时数据文件与传统的定时验证工具一起使用，以执行整个芯片单元级定时验证。

2. 发明授权

US08074190B1 Integrated circuit design systems for replacing flip-flops with pulsed latches 有权
标题翻译：用于用脉冲锁存器替换触发器的集成电路设计系统
公开(公告)号：US08074190B1
公开(公告)日：2011-12-06
申请号：US12717931
申请日：2010-03-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

3. 发明授权

US07467367B1 Method and system for clock tree synthesis of an integrated circuit 有权
标题翻译：集成电路时钟树合成方法和系统
公开(公告)号：US07467367B1
公开(公告)日：2008-12-16
申请号：US11259044
申请日：2005-10-27
申请人： Hung-Chun Li , Chien-Chu Kuo , Minghorng Lai , Ming-Chyuan Chen
发明人： Hung-Chun Li , Chien-Chu Kuo , Minghorng Lai , Ming-Chyuan Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-based clock tree estimation, wherein each block is subdivided into one or more grids. The aspects further include merging of the estimated block-level clock tree structures with the top-level clock tree synthesis.
摘要翻译：集成电路的时钟树合成方面包括执行顶层时钟树合成，以及估计集成电路的一个或多个块级时钟树结构。基于基于网格的时钟树估计来估计块级时钟树结构，其中每个块被细分成一个或多个网格。这些方面还包括将估计的块级时钟树结构与顶级时钟树合成的合并。

4. 发明授权

US08656324B2 Circuit design systems for replacing flip-flops with pulsed latches 有权
标题翻译：用脉冲锁存器代替触发器的电路设计系统
公开(公告)号：US08656324B2
公开(公告)日：2014-02-18
申请号：US13310771
申请日：2011-12-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

5. 发明申请

US20120079437A1 CIRCUIT DESIGN SYSTEMS FOR REPLACING FLIP-FLOPS WITH PULSED LATCHES 有权
标题翻译：用于更换带有脉冲锁存器的浮标的电路设计系统
公开(公告)号：US20120079437A1
公开(公告)日：2012-03-29
申请号：US13310771
申请日：2011-12-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

6. 发明授权

US07694242B1 System and method of replacing flip-flops with pulsed latches in circuit designs 失效
标题翻译：在电路设计中用脉冲锁存器代替触发器的系统和方法
公开(公告)号：US07694242B1
公开(公告)日：2010-04-06
申请号：US11609304
申请日：2006-12-11
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

7. 发明授权

US06941499B1 Method to verify the performance of BIST circuitry for testing embedded memory 失效
标题翻译：验证嵌入式内存测试BIST电路性能的方法
公开(公告)号：US06941499B1
公开(公告)日：2005-09-06
申请号：US09883449
申请日：2001-06-18
申请人： Nai-Yin Sung , Ming-Chyuan Chen
发明人： Nai-Yin Sung , Ming-Chyuan Chen
IPC分类号： G06F11/00
CPC分类号： G11C29/02 , G06F17/5022 , G06F2217/14
摘要： A new method and apparatus to verify the performance of a built-in self-test circuit for testing embedded memory in an integrated circuit device is achieved. A set of faults is introduced into an embedded memory behavior model. The embedded memory behavior model comprises a high-level language model. Each member of the set of faults comprises a finite state machine state, a memory address, and a memory data fault. The built-in self-test circuit and the embedded memory behavior model are then simulated. The built-in self-test circuit generates input data and address patterns for the embedded memory behavior model. The embedded memory behavior model outputs memory address and data in response to the input data and address patterns. The input address and data and the memory address and data are compared in the built-in self-test circuit and a fault output is generated if not matching. The fault output and the set of faults are compared to verify the performance of the built-in self-test circuit.
摘要翻译：实现了一种用于验证集成电路器件中嵌入式存储器测试的内置自检电路的性能的新方法和装置。一组故障被引入到嵌入式存储器行为模型中。嵌入式存储器行为模型包括高级语言模型。该组故障的每个成员包括有限状态机状态，存储器地址和存储器数据故障。然后对内置自检电路和嵌入式存储器行为模型进行仿真。内置自测电路为嵌入式存储器行为模型生成输入数据和地址模式。嵌入式存储器行为模型响应于输入数据和地址模式输出存储器地址和数据。在内置自检电路中比较输入地址和数据以及存储器地址和数据，如果不匹配则产生故障输出。比较故障输出和故障组，验证内置自检电路的性能。

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