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1. 发明授权

US08074190B1 Integrated circuit design systems for replacing flip-flops with pulsed latches 有权
标题翻译：用于用脉冲锁存器替换触发器的集成电路设计系统
公开(公告)号：US08074190B1
公开(公告)日：2011-12-06
申请号：US12717931
申请日：2010-03-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

2. 发明授权

US08656324B2 Circuit design systems for replacing flip-flops with pulsed latches 有权
标题翻译：用脉冲锁存器代替触发器的电路设计系统
公开(公告)号：US08656324B2
公开(公告)日：2014-02-18
申请号：US13310771
申请日：2011-12-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

3. 发明申请

US20120079437A1 CIRCUIT DESIGN SYSTEMS FOR REPLACING FLIP-FLOPS WITH PULSED LATCHES 有权
标题翻译：用于更换带有脉冲锁存器的浮标的电路设计系统
公开(公告)号：US20120079437A1
公开(公告)日：2012-03-29
申请号：US13310771
申请日：2011-12-04
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

4. 发明授权

US07694242B1 System and method of replacing flip-flops with pulsed latches in circuit designs 失效
标题翻译：在电路设计中用脉冲锁存器代替触发器的系统和方法
公开(公告)号：US07694242B1
公开(公告)日：2010-04-06
申请号：US11609304
申请日：2006-12-11
申请人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
发明人： Hung-Chun Li , Ming-Chyuan Chen , KunMing Ho
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , H03K3/012 , H03K3/356156
摘要： A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
摘要翻译：公开了用于产生能够消耗较少动态功率的电路的电路设计系统，方法和软件。特别地，电路设计方法需要修改初始电路设计，包括耦合到多个边沿触发的触发器的时钟网络，以产生使用由脉冲发生器驱动的脉冲锁存器代替至少一些人字拖。由于脉冲锁存器比边沿触发的触发器使用更少的动态功率，所以修改的电路可能消耗较少的动态功率。电路设计方法还可能需要添加用于平衡时钟网络的延迟单元以补偿由插入脉冲发生器引起的定时效应。此外，该方法还可以包括克隆禁止的时钟路径以使更多触发器符合脉冲锁存器替换的条件。

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