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    • 3. 发明授权
    • Frequency sensor for each interface of a data carrier
    • 数据载体的每个接口的频率传感器
    • US06814295B2
    • 2004-11-09
    • US09838999
    • 2001-04-20
    • Stefan PoschPeter KompanPeter ThueringerWolfgang MeindlKlaus Ully
    • Stefan PoschPeter KompanPeter ThueringerWolfgang MeindlKlaus Ully
    • G06K1906
    • G06K19/07769G06K19/07G06K19/0723G06K19/0724
    • A data carrier (4) for the transfer of communication data (KD1, KD2) via at least two interface means (11, 12), having first interface means (11) for receiving a first communication signal (KS1), and having second interface means (12) for receiving a second communication signal (KS2), and having processing means (13) to which a first clock signal (TS1) derived from the first communication signal (KS1) or a second clock signal (TS2) derived from the second communication signal (KS2) can be applied for the processing of the transferred communication data (KD1, KD2), and having reset means (21) for resetting the processing by the processing means (13), now includes a first frequency sensor (22) which is adapted to supply first frequency reset information (RI4) to the reset means (21) when a first clock frequency of the first clock signal (TS1) or the frequency (FKS1) of the first communication signal (KS1) lies below a first lower frequency threshold (FU1), and includes a second frequency sensor (23) which is adapted to supply second frequency reset information (RI5) to the reset means (21) when a second clock frequency of the second clock signal (TS2) or the frequency (FKS2) of the second communication signal (KS2) lies below a second lower frequency threshold (FU2), the reset means (21) being adapted to reset the processing by the processing means (13) when the first clock signal (TS1) is applied to the processing means (13) and the first frequency reset information (RI4) is received or when the second clock signal (TS2) is applied to the processing means (13) and the second frequency reset information (RI5) is received.
    • 一种用于经由至少两个接口装置(11,12)传送通信数据(KD1,KD2)的数据载体(4),具有用于接收第一通信信号(KS1)的第一接口装置(11),并具有第二接口 用于接收第二通信信号(KS2)的装置(12),以及具有从第一通信信号(KS1)导出的第一时钟信号(TS1)或从第一通信信号(KS1)导出的第二时钟信号(TS2)的处理装置 第二通信信号(KS2)可以应用于所传送的通信数据(KD1,KD2)的处理,并且具有用于通过处理装置(13)重新设置处理的复位装置(21),现在包括第一频率传感器 ),其适于在第一时钟信号(TS1)的第一时钟频率或第一通信信号(KS1)的频率(FKS1)位于第一时钟信号(KS1)的下方时将第一频率复位信息(RI4)提供给复位装置(21) 第一低频阈值(FU1),并且包括第二频率 传感器(23),当第二时钟信号(TS2)的第二时钟频率或第二通信信号(KS2)的频率(FKS2)为第二时钟频率时,适于向复位装置提供第二频率复位信息(RI5) 位于第二较低频率阈值(FU2)之下时,当第一时钟信号(TS1)被施加到处理装置(13)时,复位装置(21)适于复位处理装置(13)的处理, 接收频率复位信息(RI4),或者当第二时钟信号(TS2)被施加到处理装置(13)并且接收到第二频率复位信息(RI5)时。
    • 6. 发明授权
    • Output stage for a communication contact for a data carrier
    • US06581844B2
    • 2003-06-24
    • US09825275
    • 2001-04-03
    • Peter ThueringerPeter KompanKlaus UllyStefan Posch
    • Peter ThueringerPeter KompanKlaus UllyStefan Posch
    • G06K1906
    • G06K19/073
    • An output stage (22; 26; 29) of a data carrier (2; 25; 28), which output stage is connected to a communication contact (9), said data carrier being adapted to provide contactless communication via an antenna stage (13) and contact-bound communication via the communication contact (9), includes a first transistor (T1; T4) having a first control terminal (G1; G4), a first input terminal (S1; D4) and a first output terminal (D1; S4), and a second transistor (T2) having a second control terminal (G2), a second input terminal (D2) and a second output terminal (S2), and a control stage (23; 31) for supplying first control information (SI1) to the first control terminal (G1), in order to drive the first transistor (T1; T4) into its conductive state, and for supplying second control information (SI2) to the second control terminal (G2), in order to drive the second transistor (T2) into its conductive state, in which stage an internal supply voltage (VINT), derived from an antenna signal (HF) by a power supply (15) of the data carrier (2; 25; 28) during contactless communication, can be supplied to the first input terminal (S1) and a reference potential (GND) can be supplied to the second output terminal (S2), and in which the second input terminal (D2) is connected to the communication contact (9) of the data carrier (2; 25; 28). The output stage (22; 26; 29) now includes inhibit means (R; D; 30, 31, T4), which are adapted to prevent an analysis current (IA) having an analysis current strength from being fed from the communication contact (9) into the data carrier (2; 25; 28) via the first transistor (T1; T4), the analysis current (IA) having the analysis current strength being suited for the analysis of the power consumption of the data carrier (2; 25; 28) and for hacking communication data (VKD) processed in the data carrier (2; 25; 28).
    • 9. 发明授权
    • Data carrier comprising an implanted module based on a metal lead frame with a double-sided chip cover
    • 数据载体包括基于具有双面芯片盖的金属引线框的植入模块
    • US06262368B1
    • 2001-07-17
    • US09275365
    • 1999-03-24
    • Thomas RienerStefan Posch
    • Thomas RienerStefan Posch
    • H05K500
    • G06K19/07745H01L2224/48091H01L2224/48464H01L2924/00014
    • A data carrier has a chip with chip contacts, a transmission coil for contactless communication with a write/read station, a metal lead frame with a chip carrying part and contact forming parts, and a chip cover made of electrically insulating material. The transmission coil has coil contacts. The chip cover has a first cover part covering the chip at one side of the metal lead frame and a second cover part covering the other side of the metal lead frame. The second cover part has electrically conducting passages electrically connecting the coil contacts to the contact forming parts that are otherwise connected to the chip contacts. The chip carrying part and the first and second contact forming parts are electrically insulated with respect to each other and are arranged in a substantially coplanar relationship to each other.
    • 数据载体具有芯片触点芯片,用于与写/读站无接触通信的传输线圈,具有芯片承载部分的金属引线框架和触点形成部件以及由电绝缘材料制成的芯片盖。 传输线圈具有线圈触点。 芯片盖具有在金属引线框架的一侧覆盖芯片的第一盖部分和覆盖金属引线框架的另一侧的第二盖部分。 第二盖部分具有将线圈触头电连接到否则连接到芯片触点的触点形成部件的导电通道。 芯片承载部分和第一和第二接触形成部分彼此电绝缘并且以彼此基本上共面的关系布置。