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    • 1. 发明申请
    • Optoelectronic Semiconductor Chip Having a Multiple Quantum Well Structure
    • 具有多量子阱结构的光电半导体芯片
    • US20110042643A1
    • 2011-02-24
    • US12680463
    • 2008-09-12
    • Peter StaussMatthias PeterAlexander Walter
    • Peter StaussMatthias PeterAlexander Walter
    • H01L33/04
    • H01L33/06B82Y20/00H01L33/04H01L33/32H01L2924/0002H01S5/3086H01S5/34H01L2924/00
    • An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.
    • 规定了一种光电子半导体芯片,其具有包含多个量子阱结构的活动区域(20),所述有源区域包括多个连续量子阱层(210,220,230),所述有源区域包括用于产生电磁辐射的多量子阱结构。 多量子阱结构包括至少一个第一量子阱层(210),其被n导电掺杂并且布置在邻接第一量子阱层的两个n导电掺杂阻挡层(250)之间。 它包括未掺杂的第二量子阱层(220),并且被布置在邻接第二量子阱层的两个势垒层(250,260)之间,其中一个是n导电掺杂的,另一个是未掺杂的。 另外,多量子阱结构包括至少一个未掺杂的第三量子阱层(230),其布置在与第三量子阱层相邻的两个未掺杂的势垒层(260)之间。
    • 2. 发明授权
    • Optoelectronic semiconductor chip having a multiple quantum well structure
    • 具有多量子阱结构的光电半导体芯片
    • US08173991B2
    • 2012-05-08
    • US12680463
    • 2008-09-12
    • Peter StaussMatthias PeterAlexander Walter
    • Peter StaussMatthias PeterAlexander Walter
    • H01L21/20H01L21/02H01L33/00
    • H01L33/06B82Y20/00H01L33/04H01L33/32H01L2924/0002H01S5/3086H01S5/34H01L2924/00
    • An optoelectronic semiconductor chip is specified, which has an active zone (20) containing a multi quantum well structure provided for generating electromagnetic radiation, which comprises a plurality of successive quantum well layers (210, 220, 230). The multi quantum well structure comprises at least one first quantum well layer (210), which is n-conductively doped and which is arranged between two n-conductively doped barrier layers (250) adjoining the first quantum well layer. It comprises a second quantum well layer (220), which is undoped and is arranged between two barrier layers (250, 260) adjoining the second quantum well layer, of which one is n-conductively doped and the other is undoped. In addition, the multi quantum well structure comprises at least one third quantum well layer (230), which is undoped and which is arranged between two undoped barrier layers (260) adjoining the third quantum well layer.
    • 规定了一种光电子半导体芯片,其具有包含多个量子阱结构的活动区域(20),所述有源区域包括多个连续量子阱层(210,220,230),所述有源区域包括用于产生电磁辐射的多量子阱结构。 多量子阱结构包括至少一个第一量子阱层(210),其被n导电掺杂并且布置在邻接第一量子阱层的两个n导电掺杂阻挡层(250)之间。 它包括未掺杂的第二量子阱层(220),并且被布置在邻接第二量子阱层的两个势垒层(250,260)之间,其中一个是n导电掺杂的,另一个是未掺杂的。 另外,多量子阱结构包括至少一个未掺杂的第三量子阱层(230),其布置在与第三量子阱层相邻的两个未掺杂的势垒层(260)之间。
    • 4. 发明申请
    • Substrate holder
    • 基板支架
    • US20080276869A1
    • 2008-11-13
    • US12154897
    • 2008-05-28
    • Stefan BaderMatthias PeterAlexander WalterVolker Haerle
    • Stefan BaderMatthias PeterAlexander WalterVolker Haerle
    • C23C16/00
    • C23C16/4581C23C16/4583C30B25/12
    • In order to achieve an as uniform as possible temperature over the entire surface of the substrate (2) during a temperature step and, in particular, during an epitaxy method, temperature equalization structures are incorporated in a substrate holder (1), on which the substrate (2) is located. A uniform temperature distribution on the substrate surface during the deposition of a semiconductor material reduces the emission wavelength gradient of the deposited semiconductor material. The temperature equalization structures produce specific temperature inhomogenelties in the substrate holder (1), and these smooth out the temperature profile of the substrate (2). For example, a groove (4) with a cooling effect and a support step (5) which produces a gap (8) between the substrate (2) and the substrate holder (1) are integrated in the edge area of the substrate holder (1).
    • 为了在温度步骤期间,特别是在外延方法中,在衬底(2)的整个表面上实现尽可能均匀的温度,在衬底保持器(1)中并入温度均衡结构,其中 衬底(2)位于。 在沉积半导体材料期间在衬底表面上均匀的温度分布降低了沉积的半导体材料的发射波长梯度。 温度均衡结构在衬底保持器(1)中产生特定的温度不均匀性,并且这些平滑了衬底(2)的温度分布。 例如,具有冷却效果的槽(4)和在基板(2)和基板保持件(1)之间产生间隙(8)的支撑台阶(5)被集成在基板支架的边缘区域 1)。