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1. 发明授权

US07043292B2 Single or multi-mode cardiac activity data collection, processing and display obtained in a non-invasive manner 失效
标题翻译：以非侵入性方式获得的单或多模式心脏活动数据收集，处理和显示
公开(公告)号：US07043292B2
公开(公告)日：2006-05-09
申请号：US10176944
申请日：2002-06-21
申请人： Peter P. Tarjan , Chih-Cheng Lu , Walter Besio
发明人： Peter P. Tarjan , Chih-Cheng Lu , Walter Besio
IPC分类号： A61B5/402
CPC分类号： A61B8/483 , A61B5/0408 , A61B5/745 , A61B8/08 , A61B8/488
摘要： The method of presenting concurrent information about the electrical and mechanical activity of the heart using non-invasively obtained electrical and mechanical cardiac activity data from the chest or thorax of a patient comprises the steps of: placing at least three active Laplacian ECG sensors at locations on the chest or thorax of the patient; where each sensor has at least one outer ring element and an inner solid circle element, placing at least one ultrasonic sensor on the thorax where there is no underlying bone structure, only tissue, and utilizing available ultrasound technology to produce two or three-dimensional displays of the moving surface of the heart and making direct measurements of the exact sites of the sensors on the chest surface to determine the position and distance from the center of each sensor to the heart along a line orthogonal to the plane of the sensor and create a virtual heart surface; updating the measurements at a rate to show the movement of the heart's surface; monitoring at each ultrasonic sensor site and each Laplacian ECG sensor site the position and movement of the heart and the passage of depolarization wave-fronts in the vicinity; treating those depolarization wave-fronts as moving dipoles at those sites to create images of their movement on the image of the beating heart's surface; and, displaying the heart's electrical activity on the dynamically changing image of the heart's surface with the goal to display an approximation of the activation sequence on the beating virtual surface of the heart
摘要翻译：使用来自患者的胸部或胸部的非侵入式获得的电和机械心脏活动数据呈现关于心脏的电和机械活动的并发信息的方法包括以下步骤：将至少三个有源拉普拉斯ECG心电图传感器放置在患者的胸部或胸部; 其中每个传感器具有至少一个外环元件和内部实心圆形元件，将至少一个超声波传感器放置在胸部上，其中没有下面的骨结构，仅包括组织，并且利用可用的超声技术来产生二维或三维显示的心脏的移动表面，并直接测量胸部表面上传感器的精确位置，以确定沿着与传感器平面垂直的线的每个传感器的心脏到心脏的位置和距离，并创建一个虚拟心脏表面; 以显示心脏表面运动的速率更新测量值; 在每个超声波传感器位置和每个拉普拉斯ECG点位置监测心脏的位置和运动以及去极化波前的附近; 将这些去极化波前作为移动偶极子处理，以在心跳表面上形成运动图像; 并且在心脏表面的动态变化的图像上显示心脏的电活动，目的是显示心跳的虚拟表面上的激活序列的近似值

2. 发明授权

US07002177B2 Test region layout for shallow trench isolation 失效
标题翻译：浅沟槽隔离测试区域布局
公开(公告)号：US07002177B2
公开(公告)日：2006-02-21
申请号：US10701824
申请日：2003-11-05
申请人： Weng Chang , Chih-Cheng Lu , Stacey Fu , Syun-Ming Jang
发明人： Weng Chang , Chih-Cheng Lu , Stacey Fu , Syun-Ming Jang
IPC分类号： H01L23/58 , H01L27/14 , G01R31/26
CPC分类号： H01L22/34 , H01L21/76229
摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

3. 发明授权

US07872913B2 Nonvolatile analog memory 有权
标题翻译：非易失性模拟存储器
公开(公告)号：US07872913B2
公开(公告)日：2011-01-18
申请号：US12758760
申请日：2010-04-12
申请人： Cheng-Da Huang , Chih-Cheng Lu , Hsin Chen
发明人： Cheng-Da Huang , Chih-Cheng Lu , Hsin Chen
IPC分类号： G11C16/04
CPC分类号： G11C27/005 , G11C16/0441
摘要： A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a capacitor, a first current source, a second current source and a current adjuster. The first current source controlled by a voltage value at the floating gate point and generates a first current. The second current source controlled by the voltage value at the floating gate point and generates a second current. The current adjuster receives the output voltage and a reference voltage and adjusts the first current and the second current based on the output voltage and the reference voltage. The current adjuster charges or discharges the capacitor to equalize the output voltage to the reference voltage.
摘要翻译：非易失性模拟存储器具有浮动栅极点。非易失性模拟存储器包括电容器，第一电流源，第二电流源和电流调节器。第一电流源由浮动栅极点处的电压值控制并产生第一电流。第二电流源由浮动栅极点处的电压值控制并产生第二电流。电流调节器接收输出电压和参考电压，并根据输出电压和参考电压调整第一电流和第二电流。电流调节器对电容器充电或放电，以使输出电压与参考电压相等。

4. 发明申请

US20050238073A1 Spatial bandgap modifications and energy shift of semiconductor structures 有权
标题翻译：半导体结构的空间带隙修改和能量偏移
公开(公告)号：US20050238073A1
公开(公告)日：2005-10-27
申请号：US10824838
申请日：2004-04-15
申请人： Peidong Wang , Chih-Cheng Lu , Daryoosh Vakhshoori
发明人： Peidong Wang , Chih-Cheng Lu , Daryoosh Vakhshoori
IPC分类号： H01S5/00 , H01S5/028 , H01S5/0625 , H01S5/10 , H01S5/34
CPC分类号： B82Y20/00 , H01S5/028 , H01S5/06255 , H01S5/101 , H01S5/1057 , H01S5/34 , H01S5/3413 , H01S2301/04
摘要： Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.
摘要翻译：公开了具有量子阱具有第一带隙的半导体衬底，以及具有小于第二带隙的第二带隙的量子阱。公开了半导体结构，其包括具有给定带隙的量子阱的衬底，其他量子阱被修改为具有大于给定带隙的带隙。公开了半导体衬底，其包括具有量子阱的晶片，第一带隙的截面以及大于第一带隙的第二带隙的截面。提供了形成半导体衬底的方法，其包括提供具有给定带隙的晶片，在部分上沉积介电帽和快速热退火至大于给定带隙的调谐带隙。公开了半导体结构，其包括具有通过沉积帽和快速热退火而修改的量子阱的衬底，所述量子阱具有大于给定带隙的调谐带隙。公开了一种用于形成半导体衬底的方法，其包括提供具有给定带隙的量子阱的晶片，将部分上的沉积帽和快速热退火至大于给定带隙的调谐带隙。

5. 发明申请

US20090257276A1 NONVOLATILE ANALOG MEMORY 有权
标题翻译：非易失性模拟记忆
公开(公告)号：US20090257276A1
公开(公告)日：2009-10-15
申请号：US12192137
申请日：2008-08-15
申请人： Cheng-Da Huang , Chih-Cheng Lu , Hsin Chen
发明人： Cheng-Da Huang , Chih-Cheng Lu , Hsin Chen
IPC分类号： G11C27/00 , G11C16/06 , G11C7/00
CPC分类号： G11C27/005 , G11C16/0441
摘要： A nonvolatile analog memory has a floating gate point. The nonvolatile analog memory includes a first current source, a second current source, and a current adjuster. The first current source generates a first current, and the second current source generates a second current. The current adjuster turns on or turns off a current path of the second current according to a reference current and the first current. Furthermore, when the current path of the second current is turned on, the first current is adjusted according to the second current, such that the first current is equal to the reference current.
摘要翻译：非易失性模拟存储器具有浮动栅极点。非易失性模拟存储器包括第一电流源，第二电流源和电流调节器。第一电流源产生第一电流，第二电流源产生第二电流。电流调节器根据参考电流和第一电流打开或关闭第二电流的电流路径。此外，当第二电流的电流路径导通时，根据第二电流来调节第一电流，使得第一电流等于参考电流。

6. 发明申请

US20050095727A1 Test region layout for shallow trench isolation 失效
标题翻译：浅沟槽隔离测试区域布局
公开(公告)号：US20050095727A1
公开(公告)日：2005-05-05
申请号：US10701824
申请日：2003-11-05
申请人： Weng Chang , Chih-Cheng Lu , Chu-Yun Fu , Syun-Ming Jang
发明人： Weng Chang , Chih-Cheng Lu , Chu-Yun Fu , Syun-Ming Jang
IPC分类号： H01L21/762 , H01L23/544 , H01L21/66 , G01R31/26 , H01L21/76
CPC分类号： H01L22/34 , H01L21/76229
摘要： A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：公开了一种用于测试浅沟槽隔离间隙填充特性的测试区域布局。每个测试区域还包括设置在测试区域的内部部分中的至少一个测试图案。在优选实施例中，测试图案是相对于彼此不连续的正方形或更优选的两个直径相对的“L”形。要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

7. 发明授权

US06693047B1 Method for recycling semiconductor wafers having carbon doped low-k dielectric layers 失效
标题翻译：回收具有碳掺杂低k电介质层的半导体晶片的方法
公开(公告)号：US06693047B1
公开(公告)日：2004-02-17
申请号：US10324532
申请日：2002-12-19
申请人： Chih-Cheng Lu , Wen Chang , Syun-Ming Jeng
发明人： Chih-Cheng Lu , Wen Chang , Syun-Ming Jeng
IPC分类号： H01L2131
CPC分类号： H01L21/02079 , H01L21/02032 , H01L21/31111 , H01L21/31116 , H01L21/31633
摘要： A method for removing at least one carbon doped oxide layer over a surface to recycle the semiconductor process wafer including providing a semiconductor wafer including a process surface including at least one carbon doped silicon oxide layer; oxidizing the carbon doped oxide layer according to an oxidizing treatment to convert at oxidize at least a portion of the carbon doped oxide layer to produce silicon oxide; and, wet etching the silicon oxide to substantially remove the silicon oxide.
摘要翻译：一种用于在表面上去除至少一个碳掺杂氧化物层以再循环半导体工艺晶片的方法，包括提供包括至少一个碳掺杂氧化硅层的工艺表面的半导体晶片; 根据氧化处理氧化碳掺杂的氧化物层以在氧化至少一部分碳掺杂的氧化物层以转化以产生氧化硅; 并湿法蚀刻氧化硅以基本上去除氧化硅。

8. 发明授权

US08692571B2 Apparatus and method for measuring degradation of CMOS VLSI elements 有权
标题翻译：用于测量CMOS VLSI元件退化的装置和方法
公开(公告)号：US08692571B2
公开(公告)日：2014-04-08
申请号：US13183521
申请日：2011-07-15
申请人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
发明人： Fang-Shi Jordan Lai , Chih-Cheng Lu , Yung-Fu Lin , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Manoj M. Mhala
IPC分类号： G01R31/00 , G01R31/319
CPC分类号： G01R31/31924 , G01R31/2642
摘要： The reliability of an integrated circuit is inferred from the operational characteristics of sample metal oxide semiconductor (MOS) devices switchably coupled to drain/source bias and gate input voltages that are nominal, versus voltage and current conditions that elevate stress and cause temporary or permanent degradation, e.g., hot carrier injection (HCI), bias temperature instability (BTI, NBTI, PBTI), time dependent dielectric breakdown (TDDB). The MOS devices under test (preferably both PMOS and NMOS devices tested concurrently or in turn) are configured as current sources in the supply of power to a ring oscillator having cascaded inverter stages, thereby varying the oscillator frequency as a measure of the effects of stress on the devices under test, but without elevating the stress applied to the inverter stages.
摘要翻译：集成电路的可靠性是根据样品金属氧化物半导体（MOS）器件的可操作特性推断的，该器件可以切换地耦合到漏极/源极偏置和栅极输入电压，这些标称电压和电流条件会提高应力并引起临时或永久性降解，例如热载流子注入（HCI），偏置温度不稳定性（BTI，NBTI，PBTI），时间依赖介电击穿（TDDB）。所测试的MOS器件（优选同时或同时测试的PMOS和NMOS器件）被配置为向具有级联的反相器级的环形振荡器供电的电流源，从而改变振荡器频率作为应力的影响的量度在被测设备上，但不会升高施加到逆变器级的应力。

9. 发明授权

US08493259B2 Pipeline analog-to-digital converter 有权
标题翻译：管道模数转换器
公开(公告)号：US08493259B2
公开(公告)日：2013-07-23
申请号：US13311639
申请日：2011-12-06
申请人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
发明人： Fang-Shi Jordan Lai , Hsu-Feng Hsueh , Chin-Hao Chang , Cheng Yen Weng , Chih-Cheng Lu , Manoj M. Mhala , Yung-Fu Lin
IPC分类号： H03M1/34
CPC分类号： H03M1/1014 , H03M1/0695 , H03M1/168 , H03M1/44
摘要： A pipelined ADC includes a first, second, and third pairs of comparators. The first pair of comparators compare an input voltage to a first positive reference voltage and to a first negative reference voltage. The second pair of comparators compare the input voltage to a second positive reference voltage and to a second negative reference voltage. Each comparator of the first and second pairs of comparators outputs a digital signal to an encoder. A third pair of comparators compares the input voltage to a third positive reference voltage and to a third negative reference voltage, and a comparator compares the input voltage to ground. The comparator and each comparator of the third pair of comparators is configured to output respective digital signals to an encoder. A multiplying digital-to-analog converter outputs a voltage based on the input voltage, an output from the encoder, and an output of the random number generator.
摘要翻译：流水线模数转换器包括第一，第二和第三对比较器。第一对比较器将输入电压与第一正参考电压和第一负参考电压进行比较。第二对比较器将输入电压与第二正参考电压和第二负参考电压进行比较。第一和第二对比较器的每个比较器向编码器输出数字信号。第三对比较器将输入电压与第三正参考电压和第三负参考电压进行比较，比较器将输入电压与地比较。比较器和第三对比较器对的每个比较器被配置为将相应的数字信号输出到编码器。乘法数模转换器输出基于输入电压的电压，来自编码器的输出和随机数发生器的输出。

10. 发明授权

US07344905B2 Spatial bandgap modifications and energy shift of semiconductor structures 有权
标题翻译：半导体结构的空间带隙修改和能量偏移
公开(公告)号：US07344905B2
公开(公告)日：2008-03-18
申请号：US10824838
申请日：2004-04-15
申请人： Peidong Wang , Chih-Cheng Lu , Daryoosh Vakhshoori
发明人： Peidong Wang , Chih-Cheng Lu , Daryoosh Vakhshoori
IPC分类号： H01L21/00
CPC分类号： B82Y20/00 , H01S5/028 , H01S5/06255 , H01S5/101 , H01S5/1057 , H01S5/34 , H01S5/3413 , H01S2301/04
摘要： Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.
摘要翻译：公开了具有量子阱具有第一带隙的半导体衬底，以及具有小于第二带隙的第二带隙的量子阱。公开了半导体结构，其包括具有给定带隙的量子阱的衬底，其他量子阱被修改为具有大于给定带隙的带隙。公开了半导体衬底，其包括具有量子阱的晶片，第一带隙的截面以及大于第一带隙的第二带隙的截面。提供了形成半导体衬底的方法，其包括提供具有给定带隙的晶片，在部分上沉积介电帽和快速热退火至大于给定带隙的调谐带隙。公开了半导体结构，其包括具有通过沉积帽和快速热退火而修改的量子阱的衬底，所述量子阱具有大于给定带隙的调谐带隙。公开了一种用于形成半导体衬底的方法，其包括提供具有给定带隙的量子阱的晶片，将部分上的沉积帽和快速热退火至大于给定带隙的调谐带隙。

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