专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06838711B1 Power MOS arrays with non-uniform polygate length 有权
标题翻译：功率MOS阵列具有不均匀的聚合物长度
公开(公告)号：US06838711B1
公开(公告)日：2005-01-04
申请号：US10658432
申请日：2003-09-08
申请人： Peter J. Hopper , Philipp Lindorfer , Vludislav Vashchenko , Rob Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vludislav Vashchenko , Rob Drury
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L27/10
CPC分类号： H01L29/4238 , H01L29/0692 , H01L29/78
摘要： In a MOS array, current loss at distances further away from the drain and source contacts is compensated for by adjusting the length of the polygate. In an array with drain and source contacts near the middle of the structure, the length of the polygate tapers off along the width of the polygate towards both ends of the polygate.
摘要翻译：在MOS阵列中，通过调整多晶硅栅极的长度来补偿远离漏极和源极触点的距离处的电流损耗。在具有靠近结构中间的漏极和源极触点的阵列中，多晶硅栅极的长度沿着多晶硅的宽度朝着多晶硅的两端逐渐变细。

2. 发明申请

US20120326260A1 PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS 审中-公开
标题翻译：包含N和P多个半导体区域的充电平衡组的光电
公开(公告)号：US20120326260A1
公开(公告)日：2012-12-27
申请号：US13165050
申请日：2011-06-21
申请人： William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
发明人： William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
IPC分类号： H01L31/06 , H01L31/18
CPC分类号： H01L31/103 , H01L31/03529 , Y02E10/50
摘要： A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
摘要翻译：光电二极管包括形成在半导体衬底的表面中的第一端子; 形成在所述基板表面中并与所述第一端子间隔开的第二端子; 以及形成在第一端子和第二端子之间的衬底表面中的多个相邻的交替的N型和P型扩散区域。

3. 发明授权

US08324603B2 Galvanic isolation that incorporates a transformer with an optical link and that can be integrated onto a single semiconductor substrate 有权
标题翻译：具有变压器和光学链路并且可以集成到单个半导体衬底上的电隔离
公开(公告)号：US08324603B2
公开(公告)日：2012-12-04
申请号：US12862136
申请日：2010-08-24
申请人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
发明人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
IPC分类号： G02B27/00 , H01L29/00
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译：方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。

4. 发明申请

US20110174999A1 GALVANIC ISOLATION THAT INCORPORATES A TRANSFORMER WITH AN OPTICAL LINK AND THAT CAN BE INTEGRATED ONTO A SINGLE SEMICONDUCTOR SUBSTRATE 有权
标题翻译：具有光学链路的变压器并可以集成到单个半导体基板上的隔离隔离
公开(公告)号：US20110174999A1
公开(公告)日：2011-07-21
申请号：US12862136
申请日：2010-08-24
申请人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
发明人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
IPC分类号： G02B27/00 , H05K3/10
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译：方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。

5. 发明授权

US07676922B1 Method of forming a saucer-shaped half-loop MEMS inductor with very low resistance 有权
标题翻译：形成具有非常低电阻的碟形半环MEMS电感器的方法
公开(公告)号：US07676922B1
公开(公告)日：2010-03-16
申请号：US11820464
申请日：2007-06-19
申请人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
发明人： Peter J. Hopper , Peter Johnson , Kyuwoon Hwang , Philipp Lindorfer
IPC分类号： H01K3/10
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , H01L2924/0002 , Y10T29/4902 , Y10T29/49069 , Y10T29/49165 , H01L2924/00
摘要： A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
摘要翻译：微机电系统（MEMS）电感器形成为完全围绕由铁磁材料形成的磁芯结构的碟形形状。此外，可以通过将碟形MEMS电感器分成多个电隔离的MEMS电感器楔形物来形成MEMS电感器阵列。

6. 发明授权

US07262401B2 Active pixel sensor cell with integrating varactor and method for using such cell 有权
标题翻译：具有积分变容二极管的有源像素传感器单元和使用这种单元的方法
公开(公告)号：US07262401B2
公开(公告)日：2007-08-28
申请号：US11496951
申请日：2006-08-01
申请人： Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
发明人： Peter J. Hopper , Philipp Lindorfer , Mark W. Poulter , Yuri Mirgorodski
IPC分类号： H01L27/00 , H04N3/14
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
摘要翻译：包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

7. 发明授权

US07192857B1 Method of forming a semiconductor structure with non-uniform metal widths 有权
标题翻译：形成具有不均匀金属宽度的半导体结构的方法
公开(公告)号：US07192857B1
公开(公告)日：2007-03-20
申请号：US11109961
申请日：2005-04-20
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andy Strachan
IPC分类号： H01L21/3205
CPC分类号： H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
摘要翻译：功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。

8. 发明授权

US07023068B1 Method of etching a lateral trench under a drain junction of a MOS transistor 有权
标题翻译：蚀刻在MOS晶体管的漏极结下方的横向沟槽的方法
公开(公告)号：US07023068B1
公开(公告)日：2006-04-04
申请号：US10716277
申请日：2003-11-17
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenho , Peter Johnson
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenho , Peter Johnson
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/30608 , H01L21/3083 , H01L21/3086 , H01L21/76232 , H01L21/76264 , H01L29/78
摘要： In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer.
摘要翻译：在MOS晶体管中，通过在漏极下方形成横向沟槽来减小漏极电容。这通常通过使用<100>取向晶片的<110>方向的各向异性湿蚀刻工艺来完成。

9. 发明授权

US07022968B1 Optical sensor that measures the light output by the combustion chamber of an internal combustion engine 有权
标题翻译：测量内燃机燃烧室的光输出的光学传感器
公开(公告)号：US07022968B1
公开(公告)日：2006-04-04
申请号：US10690181
申请日：2003-10-21
申请人： Peter J. Hopper , Philipp Lindorfer , Michael Mian , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Michael Mian , Robert Drury
IPC分类号： H01J40/14
CPC分类号： H01T13/48 , G01M15/10
摘要： An optical sensor provides information about the burn of the fuel mixture in the combustion chamber of an internal combustion engine as well as the timing and waveform of the spark that ignites the fuel mixture in the combustion chamber. The optical sensor can be implemented as a stand-alone device, or incorporated into a spark plug.
摘要翻译：光学传感器提供关于内燃机的燃烧室中的燃料混合物的燃烧的信息以及点燃燃烧室中的燃料混合物的火花的时序和波形。光学传感器可以被实现为独立装置，或并入火花塞中。

10. 发明授权

US06798641B1 Low cost, high density diffusion diode-capacitor 有权
标题翻译：低成本，高密度扩散二极管电容器
公开(公告)号：US06798641B1
公开(公告)日：2004-09-28
申请号：US10647602
申请日：2003-08-25
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andrew Strachan
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Andrew Strachan
IPC分类号： H01G4228
CPC分类号： H01L27/0805 , H01L29/92
摘要： A multiple-layer diffusion junction capacitor structure includes multiple layers of inter-digitated P-type dopant and N-type dopant formed in a semiconductor substrate. An opening in a hard mask is formed taking care to control the angle of the sidewall using a dry, anisotropic etching process. P-type and N-type dopant are then implanted at positive and negative shallow angles, respectively, each with a different energy and dose. By utilizing the properly determined implant angles, implant energies and implant doses for each of the dopant types, a high capacitance and high density diode junction capacitor, with inter-digitated N-type and P-type regions in the vertical direction is provided.
摘要翻译：多层扩散结电容器结构包括在半导体衬底中形成的多层数字化P型掺杂剂和N型掺杂剂。形成硬掩模的开口，其中形成了使用干燥的各向异性蚀刻工艺来控制侧壁的角度。然后分别以正和负的浅角度注入P型和N型掺杂剂，每种具有不同的能量和剂量。通过利用适当确定的植入角度，提供每种掺杂剂类型的注入能量和注入剂量，高电容和高密度二极管结电容器，在垂直方向上具有数字化的N型和P型区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式